PCM1820 datasheet(84/130 Pages) TI

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8.6.2.28 CM_TOL_CFG Register (Address = 0x3A) [Reset = 0x0]

CM_TOL_CFG is shown in Figure 8-98 and described in Table 8-83.

Return to the Table 8-55.

This register is the ADC common mode configuration register

Figure 8-98. CM_TOL_CFG Register

CH1_INP_CM_TOL_CFG[1:0]

CH2_INP_CM_TOL_CFG[1:0]

RESERVED

R/W-00b

R-0000b

Table 8-83. CM_TOL_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

CH1_INP_CM_TOL_CFG[

1:0]

R/W

00b

Channel 1 input common mode variance tolerance configuration.

0d = Common mode variance tolerance for AC coupled = 100 mVpp

and DC coupled = 2.82 Vpp

1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to

peak

2d = Common Mode Tolerance of: AC/DC Coupled Input=0-

AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For

input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to

2.6V.

3d = Reserved; Don't use

5-4

CH2_INP_CM_TOL_CFG[

1:0]

R/W

00b

Channel 2 input common mode variance tolerance configuration.

0d = Common mode variance tolerance for AC coupled = 100 mVpp

and DC coupled = 2.82 Vpp

1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to

peak

2d = Common Mode Tolerance of: AC/DC Coupled Input=0-

AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For

input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to

2.6V.

3d = Reserved; Don't use

3-0

RESERVED

0000b

Reserved bits; Write only reset value

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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