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PCM1820 Datasheet(PDF) 97 Page - Texas Instruments |
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PCM1820 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 130 page ![]() 8.6.2.48 DRE_CFG0 Register (Address = 0x6D) [Reset = 0x7B] DRE_CFG0 is shown in Figure 8-118 and described in Table 8-103. Return to the Table 8-55. This register is the dynamic range enhancer (DRE) configuration register 0. Figure 8-118. DRE_CFG0 Register 7 6 5 4 3 2 1 0 DRE_LVL[3:0] DRE_MAXGAIN[3:0] R/W-0111b R/W-1011b Table 8-103. DRE_CFG0 Register Field Descriptions Bit Field Type Reset Description 7-4 DRE_LVL[3:0] R/W 0111b DRE trigger signal level threshold. 0d = Input signal level threshold is -12 dB 1d = Input signal level threshold is -18 dB 2d = Input signal level threshold is -24 dB 3d to 6d = Input signal level threshold is as per configuration 7d = Input signal level threshold is -54 dB 8d = Input signal level threshold is -60 dB 9d = Input signal level threshold is -66 dB 10d to 15d = Reserved; Don't use 3-0 DRE_MAXGAIN[3:0] R/W 1011b DRE maximum gain allowed. 0d = Maximum gain allowed is 2 dB 1d = Maximum gain allowed is 4 dB 2d = Maximum gain allowed is 6 dB 3d to 10d = Maximum gain allowed is as per configuration 11d = Maximum gain allowed is 24 dB 12d = Maximum gain allowed is 26 dB 13d to 15d = Reserved; Don't use 8.6.2.49 AGC_CFG0 Register (Address = 0x70) [Reset = 0xE7] AGC_CFG0 is shown in Figure 8-119 and described in Table 8-104. Return to the Table 8-55. This register is the automatic gain controller (AGC) configuration register 0. Figure 8-119. AGC_CFG0 Register 7 6 5 4 3 2 1 0 AGC_LVL[3:0] AGC_MAXGAIN[3:0] R/W-1110b R/W-0111b Table 8-104. AGC_CFG0 Register Field Descriptions Bit Field Type Reset Description 7-4 AGC_LVL[3:0] R/W 1110b AGC output signal target level. 0d = Output signal target level is -6 dB 1d = Output signal target level is -8 dB 2d = Output signal target level is -10 dB 3d to 13d = Output signal target level is as per configuration 14d = Output signal target level is -34 dB 15d = Output signal target level is -36 dB www.ti.com TLV320ADC6120 SBASA92A – DECEMBER 2020 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: TLV320ADC6120 |
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