PCM1820 datasheet(22/130 Pages) TI

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The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by

up to 31 cycles of the bit clock. Table 8-5 lists the programmable offset configuration settings.

Table 8-5. Programmable Offset Settings for the ASI Slot Start

P0_R8_D[4:0] : TX_OFFSET[4:0]

PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START

0 0000 = 0d (default)

The device follows the standard protocol timing without any offset.

0 0001 = 1d

Slot start is offset by one BCLK cycle, as compared to standard protocol timing.

For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to

standard protocol timing.

......

1 1110 = 30d

Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.

For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to

standard protocol timing.

1 1111 = 31d

Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to

standard protocol timing.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio

data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using

the FSYNC_POL (P0_R7_D3) register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,

which can be set using the BCLK_POL (P0_R7_D2) register bit.

8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data

first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and

each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.

Figure 8-1 to Figure 8-4 illustrate the protocol timing for TDM operation with various configurations.

N-1

N-2

N-3

N-1

N-2

N-3

N-1

N-2

N-3

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

N-2

N-3

Slot-0

(Word Length : N)

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

Figure 8-1. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)

N-1

N-2

N-3

N-1

N-2

N-3

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

Slot-0

(Word Length : N)

th Sample

(n+1)

th Sample

TX_OFFSET = 2

FSYNC

BCLK

SDOUT

Figure 8-2. TDM Mode Protocol Timing (TX_OFFSET = 2)

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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PCM1820 Datasheet(PDF) 22 Page - Texas Instruments

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