PCM1820 datasheet(20/130 Pages) TI

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8.2 Functional Block Diagram

PGA

ADC

Channel-1

Digital Filters

(Low Latency LPF,

Programmable

Biquads, AGC)

and

Dynamic Range

Enhancer (DRE)

Audio Serial

Interface (TDM,

2S, LJ)

Audio Clock Generation

PLL

(Input Clock Source -

BCLK, GPIOx, GPIx)

2C Control

Interface

BCLK

FSYNC

SDOUT

IN1M

IN1P

IN2M_GPO1

IN2P_GPI1

GPIO1

Multifunction Pins

(Digital Microphones

Interface, Interrupt, PLL

Input Clock)

PGA

ADC

Channel-2

Programmable

Microphone Bias

MICBIAS_GPI2

4-Channel Digital Microphone Filters

Regulators, Current Bias

and Voltage Reference

SDA

SCL

8.3 Feature Description

8.3.1 Serial Interfaces

This device has two serial interfaces: control and audio data. The control serial interface is used for device

configuration. The audio data serial interface is used for transmitting audio data to the host device.

8.3.1.1 Control Serial Interfaces

The device contains configuration registers and programmable coefficients that can be set to the desired values

for a specific system and application use. All registers can be accessed using I2C communication to the device.

For more information, see the Programming section.

8.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the TLV320ADC6120 on the digital audio serial

interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation,

support for I2S or left-justified protocols format, programmable data length options, very flexible master-slave

configurability for bus clock lines and the ability to communicate with multiple devices within a system directly.

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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