PCM1820 datasheet(24/130 Pages) TI

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N-1

N-2

N-1

N-2

N-1

Left

Slot-1 to Slot-3

(Word Length : N)

N-1

N-2

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

N-1

Right

Slot-1 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

N-1

N-2

Figure 8-7. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

N-1

N-2

N-1

N-2

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

N-1

N-2

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

N-1

N-2

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

Figure 8-8. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels (including left and right slots) times the programmed word length

of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater

than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high

pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots

times the data word length configured.

8.3.1.2.3 Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK

cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.

Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB

of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data

bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining

right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 8-9 to Figure

8-12 illustrate the protocol timing for LJ operation with various configurations.

N-1

N-2

N-1

N-2

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

N-1

N-2

BCLK

SDOUT

th Sample

(n+1)

th Sample

N-1

N-2

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

FSYNC

Figure 8-9. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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PCM1820 Datasheet(PDF) 24 Page - Texas Instruments

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