PCM1820 datasheet(70/130 Pages) TI

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8.6.2.8 ASI_MIX_CFG Register (Address = 0xA) [Reset = 0x0]

ASI_MIX_CFG is shown in Figure 8-78 and described in Table 8-63.

Return to the Table 8-55.

This register is the ASI input mixing configuration register.

Figure 8-78. ASI_MIX_CFG Register

ASI_MIX_SEL[1:0]

ASI_GAIN_SEL[1:0]

ASI_IN_INVER

RESERVED

R/W-00b

R/W-0b

R-0b

Table 8-63. ASI_MIX_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

ASI_MIX_SEL[1:0]

R/W

00b

ASI input (from GPIx or GPIO) mixing selection with channel data.

0d = No mixing

1d = Channel 1 and channel 2 output data mixed with ASI input data

on channel 1 (slot 0)

2d = Channel 1 and channel 2 output data mixed with ASI input data

on channel 2 (slot 1)

3d = Mixed both channel data with ASI input data independently.

Mixed asi_in_ch_1 with channel 1 output data and similarly mix

asi_in_ch_2 with channel 2 output data

5-4

ASI_GAIN_SEL[1:0]

R/W

00b

ASI input data gain selection before mixing to channel data.

0d = No gain

1d = Gain asi input data by -6dB

2d = Gain asi input data by -12dB

3d = Gain asi input data by -18dB

ASI_IN_INVERSE

R/W

Invert ASI input data before mixing to channel data.

0d = No inversion done for ASI input data

1d = ASI input data inverted before mixing with channel data

RESERVED

Reserved bit; Write only reset value

RESERVED

Reserved bit; Write only reset value

RESERVED

Reserved bit; Write only reset value

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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