PCM1820 datasheet(85/130 Pages) TI

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8.6.2.29 BIAS_CFG Register (Address = 0x3B) [Reset = 0x0]

BIAS_CFG is shown in Figure 8-99 and described in Table 8-84.

Return to the Table 8-55.

This register is the bias and ADC configuration register

Figure 8-99. BIAS_CFG Register

RESERVED

MBIAS_VAL[2:0]

RESERVED

ADC_FSCALE[1:0]

R-0b

R/W-000b

R-00b

R/W-00b

Table 8-84. BIAS_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

Reserved bit; Write only reset value

6-4

MBIAS_VAL[2:0]

R/W

000b

MICBIAS value.

0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V)

1d = Microphone bias is set to VREF x 1.096 (3.014 V, 2.740 V, or

1.507 V)

2d = Microphone bias is set to VCM = IN1M, for ADC single-ended

configuration

3d = Microphone bias is set to VCM = IN2M, for ADC single-ended

configuration

4d = Microphone bias is set to VCM = average of IN1M and IN2M,

for ADC single-ended configuration

5d = Microphone bias is set to VCM = internal crude common mode

6d = Microphone bias is set to AVDD

7d = MICBIAS configured as GPI2

3-2

RESERVED

00b

Reserved bits; Write only reset value

1-0

ADC_FSCALE[1:0]

R/W

00b

ADC full-scale setting (configure this setting based on the AVDD

supply minimum voltage used).

0d = VREF is set to 2.75 V to support 2 VRMS for the differential input

or 1 VRMS for the single-ended input

1d = VREF is set to 2.5 V to support 1.818 VRMS for the differential

input or 0.909 VRMS for the single-ended input

2d = VREF is set to 1.375 V to support 1 VRMS for the differential

input or 0.5 VRMS for the single-ended input

3d = Reserved; Don't use

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TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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