UPD16488AP datasheet(16/91 Pages) NEC

16 / 91 page

Data Sheet S15745EJ2V0DS

µµµµPD16488A

5.1.3 Serial interface

When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and

serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial

clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to

parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the

data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read

at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal

chart is shown below.

Figure 5-1. Serial Interface Signal Chart

123456789

/CS1

SCL

CS2 = H

Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.

2. The data read function is disabled during serial interface mode.

3. When using SCL wiring, take care concerning the possible effects of terminating reflection and

noise from external sources. We recommend checking operation with the actual device.

5.1.4 Chip select

The

µPD16488A has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only

when /CS1 = L and CS2 = H. When chip select is inactive, P0 to P7 are set to high impedance (invalid) and input of RS, /RD,

or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.

5.1.5 Display data RAM and on-chip register access

Because only the required cycle time (tcyc) is satisfied when accessing the

µPD16488A from the CPU, high-speed data

transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when

data is read, there is no need for dummy data except in the display memory access register (R11).

In other words, dummy data is required only when reading data from the display memory access register (R11).

Figure 5-2 illustrates this relationship.

UPD16488AP Datasheet(PDF) 16 Page - NEC