UPD16488AP datasheet(15/91 Pages) NEC

15 / 91 page

Data Sheet S15745EJ2V0DS

µµµµPD16488A

5. DESCRIPTION OF FUNCTIONS

5.1

CPU Interface

5.1.1 Selection of interface type

The

µPD16488A chip transfers data using an 8-bit bidirectional data bus (D7 to D0) or a serial data input (SI). Setting the

polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the

following table.

PSX

/RD

/WR

C86

D5 to D0

H: Parallel input

/RD

/WR

C86

D5 to D0

L: Serial input

Note1 Note1 Note1

SCL

Hi-Z Note2

Notes 1. Fixed as either High or Low.

2. Hi-Z: High impedance

5.1.2 Parallel interface

When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection

to an i80 series or M68 series CPU (see table below).

C86

/CS1

CS2

/RD

/WR

D7 to D0

H: M68 series CPU

/CS1

CS2

R,/W

D7 to D0

L: i80 series CPU

/CS1

CS2

/RD

/WR

D7 to D0

The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the

following table.

Common

M68

i80

Function

R,/W

/RD

/WR

Reads display data and registers

Writes display data and registers

Prohibited

Writes to index register

UPD16488AP Datasheet(PDF) 15 Page - NEC

UPD16488AP Datasheet(HTML) 15 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL