UPD16488AP datasheet(21/91 Pages) NEC

21 / 91 page

Data Sheet S15745EJ2V0DS

µµµµPD16488A

5.2.3 Column address circuit

When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in

Figure 5-4.

As is shown in Table 5-1, the correspondence between the display RAM's column address and segment output can be

inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the constraints

on chip layout when assembling the LCD module.

Table 5-1. Relationship between Column Address and SEG Output

SEG Output

SEG1

SEG128

00H

→

Column address

→

7FH

ADC

(D1)

17FH

←

Column address

←

00H

5.2.4 Y address circuit

As is shown in Figure 5-4, the Y address register (R4) is used to specify the display data RAM's Y address. When using

Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a

display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address

is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set

back to 00H.

5.2.5 Common scan circuit

The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control

For example, when using 1/80 duty, when COMR = L the scan direction is COM1 → COM80 and when COMR = H,

the scan direction is COM80 → COM1 using the COM80 to COM1 pins.

Table 5-2. Relationship between Common Scan Circuit and Scan Direction

0COM1

→

COM92

COMR

(D0)

1COM92

→

COM1

5.2.6 Display start line set

As is shown in Figure 5-4, display start line set specifies the Y address that corresponds to the COM1 output for displaying

the contents of display data RAM. The display start line setting register (R12) is used to specify the top line in the display.

The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line setting register.

5.2.7 Display data latch circuit

The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM.

The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched

data so that there is no effect on the data in the display data RAM.

UPD16488AP Datasheet(PDF) 21 Page - NEC

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