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UPD16488AP Datasheet(PDF) 63 Page - NEC

Part # UPD16488AP
Description  1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
PDF  91 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD16488AP Datasheet(HTML) 63 Page - NEC

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Data Sheet S15745EJ2V0DS
63
µµµµPD16488A
6.17 Blink Data Memory Access Register (R16)
The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data
is written directly to the blink data RAM.
When using reset command to reset, the contents of memory are retained.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1D7
D6
D5
D4
D3
D2
D1
D0
Data
Status
0Normal
1
Blink
Default settings (initial values set by reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
00000000
6.18 Inverted X Address Register (R17)
The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is
incremented each time the inversion RAM is accessed.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−−−−
IXA3
IXA2
IXA1
IXA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−−−−
0000
6.19 Inversion Start Line Address Register (R18)
The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion end line address register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
ISL6
ISL5
ISL4
ISL3
ISL2
ISL1
ISL0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0000000



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