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UPD16488AP Datasheet(PDF) 14 Page - NEC

Part # UPD16488AP
Description  1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
PDF  91 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD16488AP Datasheet(HTML) 14 Page - NEC

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Data Sheet S15745EJ2V0DS
14
µµµµPD16488A
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are described below.
Pin Name
Input Type
Input/output
Recommended Connection of Unused Pins
Notes
PSX
Schmitt trigger
Input
Mode setting pin.
Note 1
/CS1
Filter
Input
Connect to VSS.
−−−−
CS2
Filter
Input
Connect to VDD1.
−−−−
/RD(E)
Filter
Input
Connect to VDD1 (i80 series interface), connect to VDD1
or VSS (serial interface).
−−−−
/WR(R,/W)
Filter
Input
Connect to VDD1 or VSS (serial interface).
−−−−
C86
Schmitt trigger
Input
Mode setting pin.
Note 1
D0 to D5
Filter
Input/output
Leave open
−−−−
D6(SCL)
Filter
Input/output
−−−−−−−−
D7(SI)
Filter
Input/output
−−−−−−−−
RS
Filter
Input
Register setting pin.
Note 2
/RES
Schmitt trigger
Input
Connect to VDD1.
−−−−
CLS
Schmitt trigger
Input
Mode setting pin
Note 1
FR
CMOS
Input/output
Leave open (using master mode, M/S = H).
−−−−
FRSYNC
CMOS
Input/output
Leave open (using master mode, M/S = H).
−−−−
DOF
CMOS
Input/output
Leave open (using master mode, M/S = H).
−−−−
M/S
Schmitt trigger
Input
Mode setting pin.
Note 1
IRS
Schmitt trigger
Input
Mode setting pin.
Note 1
SIGIN1
Schmitt trigger
Input
Connect to VDD1 or VSS.
−−−−
SIGIN2
Schmitt trigger
Input
Connect to VDD1 or VSS.
−−−−
OSCIN1
Schmitt trigger
Input
−−−−−−−−
OSCIN2
Schmitt trigger
Input
Connect to VDD1 or VSS (CLS = H)
−−−−
OSCOUT
−−−−
Output
Leave open (when using external clock)
−−−−
OSCSYNC
−−−−
Output
Leave open
−−−−
TSTIFS
Schmitt trigger
Input
Connect to VSS (during normal use)
−−−−
TSTRTST
Schmitt trigger
Input
Connect to VSS (during normal use)
−−−−
TSTVIHL
Schmitt trigger
Input
Connect to VSS (during normal use)
−−−−
TESTOUT
－
Output
Leave open
Notes 1. Connect to either VDD1 or VSS, depending on the mode setting.
2. Input either VDD1 or VSS output from CPU, depending on the mode setting.



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