CP3BT13 datasheet(3/232 Pages) NSC

3 / 232 page

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2.0

Features

CPU Features

Fully static RISC processor core, capable of operating

from 0 to 24 MHz with zero wait/hold states

Minimum 41.7 ns instruction cycle time with a 24-MHz in-

ternal clock frequency, based on a 12-MHz external input

30 independently vectored peripheral interrupts

On-Chip Memory

256K bytes reprogrammable Flash program memory

8K bytes Flash data memory

10K bytes of static RAM data memory

Addresses up to 8 Mbytes of external memory

Broad Range of Hardware Communications Peripherals

Bluetooth Lower Link Controller (LLC) including a shared

4.5K byte Bluetooth RAM and 1K byte Bluetooth Se-

quencer RAM

Full CAN interface with 15 message buffers conforming

to CAN specification 2.0B active

ACCESS.bus serial bus (compatible with Philips I2C bus)

8/16-bit SPI, Microwire/Plus serial interface

Universal Asynchronous Receiver/Transmitter (UART)

Advanced Audio Interface (AAI) to connect to external 8/

13-bit PCM Codecs as well as to ISDN-Controllers

through the IOM-2 interface (slave only)

CVSD/PCM converter supporting one bidirectional audio

connection

General-Purpose Hardware Peripherals

Dual 16-bit Multi-Function Timer

Versatile Timer Unit with four subsystems (VTU)

Four channel DMA controller

Timing and Watchdog Unit

Flexible I/O

Up to 40 general-purpose I/O pins (shared with on-chip

peripheral I/O pins)

Programmable I/O pin characteristics: TRI-STATE out-

put, push-pull output, weak pull-up input, high-imped-

ance input

Schmitt triggers on general purpose inputs

Multi-Input Wakeup

Extensive Power and Clock Management Support

On-chip Phase Locked Loop

Support for multiple clock options

Dual clock and reset

Power-down modes

Power Supply

I/O port operation at 2.5V to 3.3V

Core logic operation at 2.5V

On-chip power-on reset

Temperature Range

-40°C to +85°C (Industrial)

Packages

CSP-48, LQFP-100

Complete Development Environment

Pre-integrated hardware and software support for rapid

prototyping and production

Integrated environment

Project manager

Multi-file C source editor

High-level C source debugger

Comprehensive, integrated, one-stop technical support

Bluetooth Protocol Stack

Applications can interface to the high-level protocols or

directly to the low-level Host Controller Interface (HCI)

Transport layer support allows HCI command-based in-

terface over UART port

Baseband (Link Controller) minimizes the performance

demand on the CPU

CP3BT13 Connectivity Processor Selection Guide

NSID

Speed

(MHz)

Temp. Range

Program

Flash

(kBytes)

Data

Flash

(kBytes)

SRAM

(kBytes)

External

Address

Lines

I/Os

Package

Type

CP3BT13G38

-40° to +85°C

256

LQFP-100

CP3BT13K38

-40° to +85°C

256

CSP-48

CP3BT13 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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