CP3BT13 datasheet(68/232 Pages) NSC

68 / 232 page

www.national.com

15.0 Bluetooth Controller

The integrated hardware Bluetooth Lower Link Controller

(LLC) complies to the Bluetooth Specification Version 1.1

and integrates the following functions:

4.5K-byte dedicated Bluetooth data RAM

1K-byte dedicated Bluetooth Sequencer RAM

Support of all Bluetooth 1.1 packet types

Support for fast frequency hopping of 1600 hops/s

Access code correlation and slot timing recovery circuit

Power Management Control Logic

BlueRF-compatible interface to connect with National’s

LMX5252 and other RF transceiver chips

For a detailed description of the interface to the LMX5252,

consult the LMX5252 data sheet which is available from the

National Semiconductor wireless group. National provides

software libraries for using the Bluetooth LLC. Documenta-

tion for the software libraries is also available from National

Semiconductor.

15.1

RF INTERFACE

The CP3BT13 interfaces to the LMX5251 or LMX5252 radio

chips though the RF interface.

Figure 9 shows the interface between the CP3BT13 and the

LMX5251 radio chip.

Figure 9.

LMX5251 Interface

Figure 10 shows the interface between the CP3BT13 and

the LMX5252 radio chip.

Figure 10.

LMX5252 Interface

The CP3BT13 implements a BlueRF-compatible interface,

which may be used with other RF transceiver chips.

15.1.1

RF Interface Signals

The RF interface signals are grouped as follows:

Modem Signals (BBCLK, RFDATA, and RFSYNC)

Control Signal (RFCE)

Serial Interface Signals (SCLK, SDAT, and SLE)

Bluetooth

Sequencer

Status

Signals

(BTSEQ1,

BTSEQ2, and BTSEQ2)

X1CKI/BBCLK

The X1CKI/BBCLK pin is the input signal for the 12-MHz

clock signal. The radio chip uses this signal internally as the

12× oversampling clock and provides it externally to the

CP3BT13 for use as the Main Clock.

RFDATA

The RFDATA signal is the multiplexed Bluetooth data re-

ceive and transmit signal. The data is provided at a bit rate

of 1Mbit/s with 12× oversampling, synchronized to the 12

MHz BBCLK. The RFDATA signal is a dedicated RF inter-

face pin. This signal is driven to a logic high level after reset.

RFSYNC

In receive mode (data direction from the radio chip to the

CP3BT13), the RFSYNC signal acts as the frequency cor-

rection/DC compensation circuit control output to the radio

chip. The RFSYNC signal is driven low throughout the cor-

relation phase and driven high when synchronization to the

received access code is achieved.

In transmit mode (data direction from the CP3BT13 to the

radio chip), the RFSYNC signal enables the RF output of

the radio chip. When the RFSYNC pin is driven high, the RF

CP3BT13

LMX5251

X1CKI/BBCLK

BBP_CLOCK

RFDATA

TX_RX_DATA

PI0/RFSYNC

TX_RX_SYNC

PI3/SCLK

CCB_CLOCK

PI4/SDAT

CCB_DATA

PI1/RFCE

IOVCC

VDD_DIG_IN

VCC

PI5/SLE

CCB_LATCH

DS143

CP3BT13

LMX5252

X1CKI/BBCLK

BRCLK

RFDATA

BBDATA_1

PI2/BTSEQ1

BPKTCTL

PI3/SCLK

BDCLK

PI4/SDAT

BDDATA

PI1/RFCE

BXTLEN

IOVCC

VCC

+2.8V

PI5/SLE

BDEN#

DS318

CP3BT13 Datasheet(PDF) 68 Page - National Semiconductor (TI)

CP3BT13 Datasheet(HTML) 68 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL