CP3BT13 datasheet(36/232 Pages) NSC

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WRPROT

The WRPROT field controls the global write

protection mechanism for the on-chip flash

program memory. If a majority of the three

WRPROT bits are clear, the flash program

memory is protected against write access

from any source and read access from the se-

rial debug interface. If a majority of the WR-

PROT bits are set, write access is allowed.

8.5

FLASH MEMORY INTERFACE

REGISTERS

There is a separate interface for the program flash and data

flash memories. The same set of registers exist in both in-

terfaces. In most cases they are independent of each other,

but in some cases the program flash interface controls the

interface for both memories, as indicated in the following

sections. Table 18 lists the registers.

8.5.1

Flash Memory Information Block Address

The FMIBAR register specifies the 8-bit address for read or

write access to an information block. Because only word ac-

cess to the information blocks is supported, the least signif-

icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The

hardware automatically clears the LSB, without regard to

the value written to the bit. The FMIBAR register is cleared

after device reset. The CPU bus master has read/write ac-

cess to this register.

IBA

The Information Block Address field holds the

word-aligned address of an information block

location accessed during a read or write

transaction. The LSB of the IBA field is always

clear.

8.5.2

Flash Memory Information Block Data Register

(FMIBDR/FSMIBDR)

The FMIBDR register holds the 16-bit data for read or write

access to an information block. The FMIBDR register is

cleared after device reset. The CPU bus master has read/

write access to this register.

IBD

The Information Block Data field holds the

data word for access to an information block.

For write operations the IBD field holds the

data word to be programmed into the informa-

tion block location specified by the IBA ad-

Table 18

Flash Memory Interface Registers

Program

Memory

Data

Memory

Description

FMIBAR

FF F940h

FSMIBAR

FF F740h

Flash Memory

Information Block

Address Register

FMIBDR

FF F942h

FSMIBDR

FF F742h

Flash Memory

Information Block

Address Register

FM0WER

FF F944h

FSM0WER

FF F744h

Flash Memory 0

Write Enable Register

FM1WER

FF F946h

N/A

Flash Memory 1

Write Enable Register

FMCTRL

FF F94Ch

FSMCTRL

FF F74Ch

Flash Memory

Control Register

FMSTAT

FF F94Eh

FSMSTAT

FF F74Eh

Flash Memory

Status Register

FMPSR

FF F950h

FSMPSR

FF F750h

Flash Memory

Prescaler Register

FMSTART

FF F952h

FSMSTART

FF F752h

Flash Memory Start

Time Reload Register

FMTRAN

FF F954h

FSMTRAN

FF F754h

Flash Memory

Transition Time

Reload Register

FMPROG

FF F956h

FSMPROG

FF F756h

Flash Memory

Programming Time

Reload Register

FMPERASE

FF F958h

FSMPERASE

FF F758h

Flash Memory Page

Erase Time Reload

FMMERASE0

FF F95Ah

FSMMERASE0

FF F75Ah

Flash Memory Module

Erase Time Reload

FMEND

FF F95Eh

FSMEND

FF F75Eh

Flash Memory End

Time Reload Register

FMMEND

FF F960h

FSMMEND

FF F760h

Flash Memory Module

Erase End Time

Reload Register

FMRCV

FF F962h

FSMRCV

FF F762h

Flash Memory

Recovery Time

Reload Register

FMAR0

FF F964h

FSMAR0

FF F764h

Flash Memory

Auto-Read Register 0

FMAR1

FF F966h

FSMAR1

FF F766h

Flash Memory

Auto-Read Register 1

FMAR2

FF F968h

FSMAR2

FF F768h

Flash Memory

Auto-Read Register 2

Reserved

IBA

IBD

Table 18

Flash Memory Interface Registers

Program

Memory

Data

Memory

Description

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