CP3BT13 datasheet(53/232 Pages) NSC

53 / 232 page

www.national.com

11.1

EXTERNAL CRYSTAL NETWORK

An external crystal network is connected to the X1CKI and

X1CKO pins to generate the Main Clock, unless an external

clock signal is driven on the X1CKI pin. A similar external

crystal network may be used at pins X2CKI and X2CKO for

the Slow Clock. If an external crystal network is not used for

the Slow Clock, the Slow Clock is generated by dividing the

fast Main Clock.

The crystal network you choose may require external com-

ponents different from the ones specified in this datasheet.

In this case, consult with National’s engineers for the com-

ponent specifications

The crystals and other oscillator components must be

placed close to the X1CKI/X1CKO and X2CKI/X2CKO de-

vice input pins to keep the printed trace lengths to an abso-

lute minimum.

Figure 4 shows the required crystal network at X1CKI/

X1CKO and optional crystal network at X2CKI/X2CKO.

Table 23 shows the component specifications for the main

crystal network and Table 24 shows the component specifi-

cations for the 32.768 kHz crystal network.

Figure 4.

External Crystal Network

Choose capacitor component values in the tables to obtain

the specified load capacitance for the crystal when com-

bined with the parasitic capacitance of the trace, socket, and

package (which can vary from 0 to 8 pF). As a guideline, the

load capacitance is:

C2 > C1

C1 can be trimmed to obtain the desired load capacitance.

The start-up time of the 32.768 kHz oscillator can vary from

one to six seconds. The long start-up time is due to the high

Q value and high serial resistance of the crystal necessary

to minimize power consumption in Power Save mode.

11.2

MAIN CLOCK

The Main Clock is generated by the 12-MHz high-frequency

oscillator or driven by an external signal (typically the

LMX5252 RF chip). It can be stopped by the Power Man-

agement Module to reduce power consumption during peri-

ods of reduced activity. When the Main Clock is restarted, a

14-bit timer generates a Good Main Clock signal after a

start-up delay of 32,768 clock cycles. This signal is an indi-

cator that the high-frequency oscillator is stable.

12 MHz/32.768 kHz

Crystal

GND

X1CKI/X2CKI

X1CKO/X2CKO

DS007

Table 23

Component Values of the High Frequency Crystal Circuit

Component

Parameters

Values

Tolerance

Crystal

Resonance Frequency

Type

Max. Serial Resistance

Max. Shunt Capacitance

Load Capacitance

12 MHz ± 20 ppm

AT-Cut

Ω

7 pF

22 pF

N/A

Capacitor C1, C2

Capacitance

22 pF

20%

Table 24

Component Values of the Low Frequency Crystal Circuit

Component

Parameters

Values

Tolerance

Crystal

Resonance Frequency

Type

Maximum Serial Resistance

Maximum Shunt Capacitance

Load Capacitance

Min. Q factor

32.768 kHz

Parallel

N-Cut or XY-bar

40 k

Ω

2 pF

12.5 pF

40000

N/A

Capacitor C1, C2

Capacitance

25 pF

20%

---------------------

Cparasitic

CP3BT13 Datasheet(PDF) 53 Page - National Semiconductor (TI)

CP3BT13 Datasheet(HTML) 53 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL