CP3BT13 datasheet(39/232 Pages) NSC

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DERR

The Data Loss Error bit indicates that a buffer

overrun has occurred during a programming

sequence. After a data loss error occurs, soft-

ware can clear the DERR bit by writing a 1 to

it. Writing a 0 to the DERR bit has no effect.

Software must not change this bit while the

flash program memory is busy being pro-

grammed or erased.

– No data loss error occurred.

– Data loss error occurred.

8.5.8

Flash Memory Prescaler Register (FMPSR/

FSMPSR)

The FMPSR register is a byte-wide read/write register that

selects the prescaler divider ratio. The CPU must not modify

this register while an erase or programming operation is in

progress (FMBUSY is set). At reset, this register is initial-

ized to 04h if the flash memory is idle. The CPU bus master

has read/write access to this register.

FTDIV

The prescaler divisor scales the frequency of

the System Clock by a factor of (FTDIV + 1).

8.5.9

Flash Memory Start Time Reload Register

(FMSTART/FSMSTART)

The FMSTART/FSMSTART register is a byte-wide read/

write register that controls the program/erase start delay

time. Software must not modify this register while a pro-

gram/erase operation is in progress (FMBUSY set). At re-

set, this register is initialized to 18h if the flash memory is

idle. The CPU bus master has read/write access to this reg-

ister.

FTSTART

The Flash Timing Start Delay Count field gen-

erates a delay of (FTSTART + 1) prescaler

output clocks.

8.5.10

Flash Memory Transition Time Reload

The FMTRAN/FMSTRAN register is a byte-wide read/write

Software must not modify this register while program/erase

operation is in progress (FMBUSY set). At reset, this regis-

ter is initialized to 30h if the flash memory is idle. The CPU

bus master has read/write access to this register.

FTTRAN

The Flash TIming Transition Count field spec-

ifies a delay of (FTTRAN + 1) prescaler output

clocks.

8.5.11

Flash Memory Programming Time Reload

The FMPROG/FSMPROG register is a byte-wide read/write

ware must not modify this register while a program/erase

operation is in progress (FMBUSY set). At reset, this regis-

ter is initialized to 16h if the flash memory is idle. The CPU

bus master has read/write access to this register.

FTPROG

The Flash Timing Programming Pulse Width

field specifies a programming pulse width of

8 × (FTPROG + 1) prescaler output clocks.

8.5.12

Flash Memory Page Erase Time Reload

The FMPERASE/FSMPERASE register is a byte-wide

read/write register that controls the page erase pulse width.

Software must not modify this register while a program/

erase operation is in progress (FMBUSY set). At reset, this

CPU bus master has read/write access to this register.

FTPER

The Flash Timing Page Erase Pulse Width

field specifies a page erase pulse width of

4096

× (FTPER + 1) prescaler output clocks.

Reserved

FTDIV

FTSTART

FTTRAN

FTPROG

FTPER

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