CP3BT13 datasheet(63/232 Pages) NSC

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13.1.5

Wake-Up Interrupt Control Register 2

(WKICTL2)

The WKICTL2 register is a word-wide read/write register

that selects the interrupt request signal for the associated

MIWU channels WUI15 to WUI8. At reset, the WKICTL2

for all eight channels. The register format is shown below.

WKINTR

The Wake-Up Interrupt Request Select fields

select which of the four MIWU interrupt re-

quests are activated for the corresponding

channel.

00 – Selects MIWU interrupt request 0.

01 – Selects MIWU interrupt request 1.

10 – Selects MIWU interrupt request 2.

11 – Selects MIWU interrupt request 3.

13.1.6

Wake-Up Pending Register (WKPND)

The WKPND register is a word-wide read/write register in

which the Multi-Input Wake-Up module latches any detect-

ed trigger conditions. The CPU can only write a 1 to any bit

position in this register. If the CPU attempts to write a 0, it

has no effect on that bit. To clear a bit in this register, the

CPU must use the WKPCL register. This implementation

prevents a potential hardware-software conflict during a

read-modify-write operation on the WKPND register.

This register is cleared upon reset. The register format is

shown below.

WKPD

The Wake-Up Pending bits indicate which

MIWU channels have been triggered. The

WKPD[15:0] bits correspond to the WUI[15:0]

channels. Writing 1 to a bit sets it.

– Trigger condition did not occur.

– Trigger condition occurred.

13.1.7

Wake-Up Pending Clear Register (WKPCL)

The Wake-Up Pending Clear (WKPCL) register is a word-

wide write-only register that lets the CPU clear bits in the

WKPND register. Writing a 1 to a bit position in the WKPCL

Writing a 0 has no effect. Do not modify this register with in-

structions that access the register as a read-modify-write

operand, such as the bit manipulation instructions.

Reading this register location returns undefined data.

Therefore, do not use a read-modify-write sequence (such

as the SBIT instruction) to set individual bits. Do not attempt

to read the register, then perform a logical OR on the regis-

ter value. Instead, write the mask directly to the register ad-

dress. The register format is shown below.

WKCL

Writing 1 to a bit clears it.

– Writing 0 has no effect.

– Writing 1 clears the corresponding bit in

the WKPD register.

13.2

PROGRAMMING PROCEDURES

To set up and use the Multi-Input Wake-Up function, use the

following procedure. Performing the steps in the order

shown will prevent false triggering of a wake-up condition.

This same procedure should be used following a reset be-

cause the wake-up inputs are left floating, resulting in un-

known data on the input pins.

1. Clear the WKENA register to disable the MIWU chan-

nels.

2. Write the WKEDG register to select the desired type of

edge sensitivity (clear for rising edge, set for falling

edge).

3. Set all bits in the WKPCL register to clear any pending

bits in the WKPND register.

4. Set up the WKICTL1 and WKICTL2 registers to define

the interrupt request signal used for each channel.

5. Set the bits in the WKENA register corresponding to

the wake-up channels to be activated.

To change the edge sensitivity of a wake-up channel, use

the following procedure. Performing the steps in the order

shown will prevent false triggering of a wake-up/interrupt

condition.

1. Clear the WKENA bit associated with the input to be re-

programmed.

2. Write the new value to the corresponding bit position in

the WKEDG register to reprogram the edge sensitivity

of the input.

3. Set the corresponding bit in the WKPCL register to

clear the pending bit in the WKPND register.

4. Set the same WKENA bit to re-enable the wake-up

function.

15 14 13 12 11 10 9

WKIN

TR15

WKIN

TR14

WKIN

TR13

WKIN

TR12

WKIN

TR11

WKIN

TR10

WKIN

TR9

WKIN

TR8

WKPD

WKCL

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