CP3BT13 datasheet(71/232 Pages) NSC

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Figure 16.

32-Bit Write Timing

Figure 17.

32-Bit Read Timing

An example of a 32-bit write is shown in Table 32. In this ex-

ample, the 32-bit value FFFF DC04h is written to register

address 0Ah. In cycle 1, the high word (FFFFh) is written. In

the first part of cycle 2, the CP3BT13 drives the header, R/

W bit, and register address for a read cycle. In the second

part of cycle 2, the LMX5252 drives the counter value. The

counter value is 0, which indicates one word has been writ-

ten. In cycle 3, the low word (DC04h) is written. In the first

part of cycle 4, the CP3BT13 drives the header, R/W bit,

and register address for a read cycle. In the second part of

cycle 4, the LMX5252 drives the counter value. The counter

value is 1, which indicates two words have been written.

SLE

SCLK

SDAT

DS322

D16

D30

D31

D14

D15

>500 ns

SLE

SCLK

SDAT

DS323

D16

D31

D15

>500 ns

Table 32

Example of 32-Bit Write with Interleaved Reads

Cycle

Serial Data on SDAT

Description

101 0 01010 1111111111111111 Write cycle driven by CP3BT13. Data is FFFFh. Address is 0Ah.

101 1 01010

First part of read cycle driven by CP3BT13. Address is 0Ah.

0000000000000000 Second part of read cycle driven by LMX5252. Counter value is 0.

101 0 01010 1101110000000100 Write cycle driven by CP3BT13. Data is DC04h. Address is 0Ah.

101 1 01010

First part of read cycle driven by CP3BT13. Address is 0Ah.

0000000000000001 Second part of read cycle driven by LMX5252. Counter value is 1.

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