PC8374L datasheet(109/239 Pages) NSC

109 / 239 page

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Revision 1.1

5.0

LPC Bus Interface

With the exception of the Glue Functions, the host can access all the functional blocks of the PC8374L device through the

LPC bus.

5.1 OVERVIEW

The LPC host interface supports I/O Read and Write, Memory Read and Write, 8-bit Firmware Memory Read and Write, and

8-bit DMA transactions, as defined in Intel’s LPC Interface Speciﬁcation, Revision 1.1.

5.2 LPC TRANSACTIONS

The LPC interface of the PC8374L device responds to the following LPC transactions:

• I/O read and write cycles

• Memory read and write cycles

• 8-bit Firmware Memory read and write

• 8-bit DMA read and write cycles

• DMA request

5.3 INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from internal IRQ sources into serial in-

terrupt request data transmitted over the SERIRQ bus. This enables devices that support only parallel IRQs to be integrated

into a system that supports only serial IRQs like the LPC bus.

Each internal IRQ is fed into a Mapping, Enable and Polarity Control block, which maps the IRQ to its associated IRQ num-

bers (see Table 14 on page 41). The resulting IRQs are then fed into the Interrupt Serializer, where they are translated into

serial data and then transmitted over the SERIRQ bus. Each interrupt number is assigned a time slot in the SERIRQ frame.

Different IRQ sources in the PC8374L device cannot share the same interrupt number and thus cannot share the same time

slot in the SERIRQ frame.

When a transition is detected on an IRQ source, the new value of the IRQ source is transmitted over the SERIRQ bus during

the corresponding IRQ slot. For example, when a transition on the Serial Port IRQ is detected, the new value of the Serial

Port IRQ is transmitted during time slot n of the SERIRQ bus.

Winbond Electronics Corp. Advanced PC Product Center

PC8374L Datasheet(PDF) 109 Page - National Semiconductor (TI)