PC8374L datasheet(112/239 Pages) NSC

112 / 239 page

6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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112

Revision1.1

The GPCFG2 register controls the Load Protection configuration option:

• V

DD-Powered Load: Disables the Output Buffer (if enabled), the Static Pull-Up (if enabled), the Static Pull-Down (if en-

abled) and the Input Buffer if the specific GPIO pin is connected to a VDD-powered device and VDD3 power to the

PC8374L is not present (No_Vdd). This function is controlled by the VDD-powered Load bit (bit 4).

6.2.2

Operation

If the output is enabled, the value that is written to the GPDO or GPDIO registers is driven to the pin. Reading from the GPDO

The GPDI register is a read-only register. Reading from the GPDI register returns the actual pin value regardless of its

source (the port itself or an external device). Writing to this register is ignored.

Reading from the GPDIO register returns the actual pin value regardless of its source.

Activation of the GPIO module is controlled by device-specific configuration bits. When this module is inactive, access

through the LPC bus to the runtime registers (GPDI, GPDO and GPDIO) is disabled; however, there is no change in the

GPDO and GPDIO values and therefore there is no effect on the outputs of the pins.

The configuration and data registers of each GPIO pin are reset according to the setting of VDDLOAD bit in GPCFG2 reg-

ister (see Section 3.14.6 on page 77).

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PC8374L Datasheet(PDF) 112 Page - National Semiconductor (TI)