PC8374L datasheet(115/239 Pages) NSC

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6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

Revision 1.1

115

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6.4 GPIO PORT REGISTERS

The following abbreviations are used to indicate the Register Type:

● R/W

= Read/Write.

● R

= Read from register (data written to this address is sent to a different register).

● W

= Write (see above).

● RO

= Read-only.

● WO

= Write-only. Reading from the bit returns 0.

● R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

● R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

6.4.1

GPIO Pin Configuration Registers Structure

For each GPIO Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO

pin. The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see

Section 3.14.3 on page 75), which functions as an index register for the pin, and the selected GPCFG1, GPEVR and GPCFG2

registers, which reflect the configuration of the currently selected pin (see Table 43). All of these registers are VSB3 powered.

6.4.2

GPIO Port Runtime Register Map

All of these registers are VSB3 powered.

Table 43. GPIO Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Power Well

Reset

F0h

GPIO Pin Select register (GPSEL)

R/W

VSB3

00h

F1h

GPIO Pin Conﬁguration register 1 (GPCFG1)

Varies per bit

VSB3

40h

F2h

GPIO Pin Event Routing register (GPEVR)

R/W or RO

VSB3

01h

F3h

GPIO Pin Conﬁguration register 2 (GPCFG2)

R/W or RO

VSB3

00h

F8h

GPIO Mode Select register (GPMODE)

R/W or RO

VSB3

01h

Table 44. GPIO Port Runtime Register Map

Offset

Mnemonic

Type

Power Well Reset

Section

SEPDIO1 =1

1. See Section 3.14.7 on page 78.

SEPDIO = 0

Device speciﬁc2

2. The location of this register is deﬁned in Section 3.14.1 on page 73.

GPDO

GPIO Data Out

R/W

VSB3

FFh

6.4.3

Device speciﬁc2

GPDI

GPIO Data In

VSB3

−

6.4.4

Device speciﬁc2

GPEVEN

GPIO Event Enable

R/W

VSB3

00h

6.4.5

Device speciﬁc2

GPEVST

GPIO Event Status

R/W1C

VSB3

00h

6.4.6

Device speciﬁc2

GPDIO

GPIO Data In/Out

R/W

VSB3

FFh3

3. The data read from this register after reset is undeﬁned.

6.4.7

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