PC8374L datasheet(111/239 Pages) NSC

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6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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The functionality of the GPIO port is divided into:

• Basic functionality: Includes configuration of, writing to and reading from the GPIO pins (described in Section 6.2)

• Enhanced functionality: Includes wake-up event detection and system notification (described in Section 6.3)

In addition, the GPIO port can be operated in one of the following modes:

• Separate Data I/O: Separate registers are available for Data In (GPDI) and for Data Out (GPDO) in addition to the Data

In/Out register (GPDIO) and to the enhanced functionality registers (GPEVST and GPEVEN).

• Common Data I/O: Only the Data In/Out register (GPDIO) is available.

6.2 BASIC FUNCTIONALITY

The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and

GPDI (or GPDIO). The configuration and operation of a single pin GPIOXn (pin ‘n’ in port ‘X’) is shown in Figure 16 (note

that for clarity, the static pull-down resistor is not shown):

Figure 16. GPIO Basic Functionality

6.2.1

Configuration Options

The GPCFG1 register controls the following basic configuration options, as shown in Figure 16:

• Port Direction: Controlled by Output Enable (bit 0).

• Output Type: Push-pull vs. open-drain; it is controlled by Output Buffer Type (bit 1) by enabling/disabling the upper tran-

sistor of the output buffer.

• Static Pull-Up: May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2)

• Pin Lock: GPIO pin may be locked to prevent any changes in the output value and/or the output configuration. The lock

is controlled by bit 3. It disables writes to GPDO and GPDIO registers bits, to bits 7, 3

−0 of GPCFG1 register (including

the Lock bit itself) and to bit 4 of GPCFG2 register.

Data Out

Data In

Output

Enable

Output

Lock

Type

Static

Pull-Up

Push-Pull =1

Pull-Up

Control

Read-only

Read/Write

(Bit 3)

(Bit 2)

(Bit 1)

(Bit 0)

Lock

(GPCFG1)

LPC Bus

(GPDI)

(GPDO)

Lock

VDD-Powered

Load

(Bit 4)

Lock

(GPCFG2)

No_Vdd

GPIO Pin Conﬁguration Registers 1 and 2

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PC8374L Datasheet(PDF) 111 Page - National Semiconductor (TI)

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