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PC8374L Datasheet(PDF) 123 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC8374L
Description  SensorPathTM SuperI/O with Glue Functions
PDF  239 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC8374L Datasheet(HTML) 123 Page - National Semiconductor (TI)

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7.0 Glue Functions (Continued)
Revision 1.1
123
www.national.com
7.2.4
Main Power Good
This function generates the PWRGD_3V signal, indicating that the Main power supply voltage is valid. The PWRGD_3V sig-
nal indicates to system components that their input power supplies are valid. PWRGD_3V is de-asserted immediately when
SLP_S3 is asserted or PWRGD_PS is de-asserted. It is asserted with tPSD delay after PWRGD_PS is asserted. Figure 24
shows a simplified diagram of the circuit that generates the PWRGD_3V signal.
Figure 24. PWRGD_3V Generation (Simplified Diagram)
For the AC characteristics, see “Main Power Good” on page 234.
7.2.5
Power Distribution Control
This function generates the BKFD_CUT and the LATCHED_BF_CUT power distribution control signals.
An active low BKFD_CUT signal is generated when the Main power supply voltage is valid (PWRGD_PS = high) and the
system is not in one of the S3 to S5 sleep states (SLP_S3 = high).
The LATCHED_BF_CUT signal is generated from BKFD_CUT and SLP_S5 as follows:
● Rising edge of BKFD_CUT while the system is not in S5 sleep state (SLP_S5 = high) sets LATCHED_BF_CUT to
high.
● Falling edge of BKFD_CUT while the system is not in S5 sleep state (SLP_S5 = high) resets LATCHED_BF_CUT to
low.
● When the system is in S5 sleep state (SLP_S5 = low), LATCHED_BF_CUT is reset to low.
Figure 25 shows a simplified diagram of the circuit that generates the BKFD_CUT and the LATCHED_BF_CUT signals.
Table 47. Resume Reset Circuit DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
VTRIP
VSB5 Threshold Level
VSB3 = 3.3V ±10%
4.05
4.5
V
ZOFF
Output Impedance at VSB3 Off
1
1. Not tested. Guaranteed by characterization.
VSB3 = 0V,
VSB5 =5V ±10%
710
K
Ω
PWRGD_PS
PWRGD_3V
Detector
tPSD
Delay
Reset
R-S Flip-Flop
Set
Q
SLP_S3
Winbond Electronics Corp. Advanced PC Product Center



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