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PC8374L Datasheet(PDF) 125 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 125 Page - National Semiconductor (TI) |
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125 / 239 page ![]() 7.0 Glue Functions (Continued) Revision 1.1 125 www.national.com 7.2.7 Hard-Disk LED Indicator Control This function generates the HD_LED signal, which controls the Hard Drive, red LED indicator. The Hard Drive LED is turned on by an active low HD_LED signal, generated when at least one of the PRIMARY_HD or SECONDARY_HD or SCSI pins is active (low). Figure 27 shows a simplified diagram of the circuit that generates the HD_LED signal. Figure 27. HD_LED Generation (Simplified Diagram) 7.2.8 SMBus Voltage Translation This function performs “passive” level translation between the VDD3-powered (or 2.5V-powered) CC_DDCSCL and CC_DDCSDA signals and the VDD5-powered 5V_DDCSCL and 5V_DDCSDA signals, respectively, for interfacing the Data Display Channel. The signals connected to the CC_DDCSCL, CC_DDCSDA, 5V_DDCSCL and 5V_DDCSDA pins are compatible with Intel's SMBus (Specification Rev 1.1, Dec. 11, 1998) two-wire synchronous serial interface specifications. The CC_DDCSCL and 5V_DDCSCL pins are connected through a switch. This switch is controlled by a Level Translation Control circuit, according to the voltage levels at the CC_DDCSCL and 5V_DDCSCL pins (for the DC characteristics, see Section 10.2.12 on page 216): ● For V IN <VISC at either pin, the switch is closed; therefore, both pins (CC_DDCSCL, and 5V_DDCSCL) are held at low level. ● For V IN >VISO at both pins, the switch is open; therefore, each pin is pulled up to high level by the external resistor connected to VDD3 or VDD25 (2.5V Main Power) (for the CC_DDCSCL pin) and to VDD5 (for the 5V_DDCSCL pin). In addition, when the VDD3 power is off, the switch is open, regardless of the voltage levels at the CC_DDCSCL and 5V_DDCSCL pins. The CC_DDCSDA and 5V_DDCSDA pins are connected through a similar level translation circuit and behave like CC_DDCSCL and 5V_DDCSCL. Figure 28 shows simplified a diagram of the circuit that performs SMBus voltage translation. Figure 28. SMBus Voltage Translation for VDD3 Tolerant Chipset Cluster (Simplified Diagram) 220 Ω HD_LED VDD3 Pin SCSI PRIMARY_HD LED SECONDARY_HD 2.2 K Ω 5V_DDCSnn VDD5 Pin 4.7 K Ω CC_DDCSnn VDD3 or VDD25 Pin Snn = SCL or SDA S Level Control Translation Winbond Electronics Corp. Advanced PC Product Center |
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