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PC8374L Datasheet(PDF) 164 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC8374L
Description  SensorPathTM SuperI/O with Glue Functions
PDF  239 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC8374L Datasheet(HTML) 164 Page - National Semiconductor (TI)

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8.0 Health Management (HM) (Continued)
www.national.com
164
Revision1.1
8.5.23 Status Register 1
Event status register 1. This register is accessible only through SMBus.
Note: All status bits in this register are reset when START bit of the Configuration register is reset.
Location: 41h
Type:
RO
0
R/W
START. When this bit is reset to 0, monitoring and FANPWM output control functions based on the limit
and parameter registers are disabled, and all status bits in Status Registers 1,2 and 3 are cleared. In this
case, all registers not locked by LOCK can be modified, but they do not affect the Health monitor and
control functions of the HM. START bit is always writable regardless of LOCK bit.
When this bit is set to 1, Monitoring and FANPWM output control functions based on limit and parameter
registers are enabled.
START bit is reset to 0 by a VSB Power-Up reset. Then, HM performs the following:
• After READY bit becomes 1, Temperature Zone1 is monitored (although START bit is 0). If a temper-
ature above +110
°C is detected, ETC is asserted (see Section 8.2.10 on page 139), which turns the
Main power supply off.
• The FANPWM outputs are at 0% duty cycle; they are set to a different value after either of the follow-
ing occurs:
— Two seconds elapsed since the VDD3 power has been turned on (FANPWM outputs are set to the
value contained in the associated FANPWMn MAX Duty registers)
— START bit is set to 1
Bit
76543210
Name
STAT_REG2
_ERR
ZONE3_ERR ZONE2_ERR ZONE1_ERR
5V_ERR
3.3V_ERR
Vccp_ERR
2.5V_ERR
Reset
00000000
Bit
Description
7
STAT_REG2_ERR. Is set to 1 if one of the bits in Status Register 2 is set. Once set, the bit is cleared only
after the Status Register 2 is read and then, the Status Register 1 is read.
0: No event is set in Interrupt Status Register 2 (default)
1: At least one of the event bits in Status Register 2 is set
6
ZONE3_ERR. Is set to 1 when Zone3 temperature is less than the limit set in the corresponding Low Temp
register (see Section 8.5.41 on page 172) or greater than the limit set in the corresponding High Temp
register (see Section 8.5.42 on page 172). Once set, the bit is updated again only after this register is read.
0: Temperature does not exceed any respective (default)
1: Temperature exceeds a respective limit
5
ZONE2_ERR. Is set to 1 when Zone2 temperature is less than the limit set in the corresponding Low Temp
register (see Section 8.5.39 on page 171) or greater than the limit set in the corresponding High Temp
register (see Section 8.5.40 on page 172). Once set, the bit is updated again only after this register is read.
0: Temperature does not exceed any respective limit (default)
1: Temperature exceeds a respective limit
4
ZONE1_ERR. Is set to 1 when Zone1 temperature is less than the limit set in the corresponding Low Temp
register (see Section 8.5.37 on page 171) or greater than the limit set in the corresponding High Temp
register (see Section 8.5.38 on page 171). Once set, the bit is updated again only after this register is read.
0: Temperature does not exceed any respective limit (default)
1: Temperature exceeds a respective limit
Bit
Type
Description
Winbond Electronics Corp. Advanced PC Product Center



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