PC8374L datasheet(166/239 Pages) NSC

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8.0 Health Management (HM) (Continued)

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166

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8.5.25 Status Register 3

Event status register 3. This register is accessible only through SMBus.

Note: All status bits in this register are reset when START bit of the Configuration register is reset.

Location: 73h

Type:

FAN3_STALL. Is set to 1 when Fan 3 is either stalled or running at low speed (according to the FSTLMD bit in

the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is

updated again only after this register is read.

0: Fan operating normally (default)

1: Fan is either stalled or running at low speed

FAN2_STALL. Is set to 1 when Fan 2 is either stalled or running at low speed (according to the FSTLMD bit in

the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is

updated again only after this register is read.

0: Fan operating normally (default)

1: Fan is either stalled or running at low speed

FAN1_STALL. Is set to 1 when Fan 1 is either stalled or running at low speed (according to the FSTLMD bit in

the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is

updated again only after this register is read.

0: Fan operating normally (default)

1: Fan is either stalled or running at low speed

DEV1_Fault (Device 1 Fault). Is set to 1 when a communication problem with the LM96011, LM96010 or

LM96012 device occurs. Once set, the bit is updated again only after this register is read.

0: Communication with LM96011/LM96010/LM96012 is functional (default)

1: Communication problem with LM96011/LM96010/LM96012

12V_ERR. Is set to 1 when 12V input voltage is less than the limit set in the corresponding Low Limit register

(see Section 8.5.35 on page 170) or greater than the limit set in the corresponding High Limit register (see

Section 8.5.36 on page 170). Once set, the bit is updated again only after this register is read.

0: Voltage does not exceed any respective limit (default)

1: Voltage exceeds a respective limit

Bit

76543210

Name

Reserved

CRIT3_ERR CRIT2_ERR CRIT1_ERR

Reset

00000000

Bit

Description

7-3

Reserved.

CRIT3_ERR. Is set to 1 when Zone3 temperature is more than the limit set in the corresponding

Temperature Critical Limit register (see Section 8.5.53 on page 175). Once set, the bit is updated again only

after this register is read.

0: Temperature does not exceed the critical limit (default)

1: Temperature exceeds the critical limit

CRIT2_ERR. Is set to 1 when Zone2 temperature is more than the limit set in the corresponding

Temperature Critical Limit register (see Section 8.5.52 on page 175). Once set, the bit is updated again only

after this register is read.

0: Temperature does not exceed the critical limit (default)

1: Temperature exceeds the critical limit

Bit

Description

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PC8374L Datasheet(PDF) 166 Page - National Semiconductor (TI)

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