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AD9161BBCZ Datasheet(PDF) 135 Page - Analog Devices |
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AD9161BBCZ Datasheet(HTML) 135 Page - Analog Devices |
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135 / 144 page  Data Sheet AD9161/AD9162 Rev. D | Page 135 of 144 Hex. Addr. Name Bits Bit Name Settings Description Reset Access Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x495 ECNT_STAT5 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA5 This output indicates if Lane 5 is enabled. 0x0 R 0 Lane 5 is held in soft reset. 1 Lane 5 is enabled. [2:0] ECNT_TCR5 Terminal count reached indicator of error counters for Lane 5. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows: 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x496 ECNT_STAT6 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA6 This output indicates if Lane 6 is enabled. 0x0 R 0 Lane 6 is held in soft reset. 1 Lane 6 is enabled. [2:0] ECNT_TCR6 Terminal count reached indicator of error counters for Lane 6. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows: 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x497 ECNT_STAT7 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA7 This output indicates if Lane 7 is enabled. 0x0 R 0 Lane 7 is held in soft reset. 1 Lane 7 is enabled. [2:0] ECNT_TCR7 Terminal count reached indicator of error counters for Lane 7. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows: 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x498 BD_CNT0 [7:0] BD_CNT0 Bad disparity 8-bit error counters for Lane 0. 0x0 R 0x499 BD_CNT1 [7:0] BD_CNT1 Bad disparity 8-bit error counters for Lane 1. 0x0 R 0x49A BD_CNT2 [7:0] BD_CNT2 Bad disparity 8-bit error counters for Lane 2. 0x0 R 0x49B BD_CNT3 [7:0] BD_CNT3 Bad disparity 8-bit error counters for Lane 3. 0x0 R |
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