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AD9161BBCZ Datasheet(PDF) 134 Page - Analog Devices |
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AD9161BBCZ Datasheet(HTML) 134 Page - Analog Devices |
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134 / 144 page  AD9161/AD9162 Data Sheet Rev. D | Page 134 of 144 Hex. Addr. Name Bits Bit Name Settings Description Reset Access 0x491 ECNT_STAT1 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA1 This output indicates if Lane 1 is enabled. 0x0 R 0 Lane 1 is held in soft reset. 1 Lane 1 is enabled. [2:0] ECNT_TCR1 Terminal count reached indicator of error counters for Lane 1. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows. 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x492 ECNT_STAT2 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA2 This output indicates if Lane 2 is enabled. 0x0 R 0 Lane 2 is held in soft reset. 1 Lane 2 is enabled. [2:0] ECNT_TCR2 Terminal count reached indicator of error counters for Lane 2. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows. 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x493 ECNT_STAT3 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA3 This output indicates if Lane 3 is enabled. 0x0 R 0 Lane 3 is held in soft reset. 1 Lane 3 is enabled. [2:0] ECNT_TCR3 Terminal count reached indicator of error counters for Lane 3. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows: 0x0 R Bit 2 = unexpected K (UEK) character error. Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). 0x494 ECNT_STAT4 [7:4] RESERVED Reserved. 0x0 R 3 LANE_ENA4 This output indicates if Lane 4 is enabled. 0x0 R 0 Lane 4 is held in soft reset. 1 Lane 4 is enabled. [2:0] ECNT_TCR4 Terminal count reached indicator of error counters for Lane 4. Set to 1 when the corresponding counter terminal count value of 0xFF has been reached. Counters of each lane are addressed as follows: 0x0 R |
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