PT2000 datasheet(65/148 Pages) NXP

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NXP Semiconductors

PT2000

7.5.1

MBIST

The MBIST is started by writing the MBIST password (B157h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)).

The overall MBIST operation takes about 2.2 ms (at 24 MHz) to complete. During the memory BIST five different tests are performed using

different patterns to test the RAM. The patterns are:

• All 00, All 11

• All 55, All AA

• All 0F, All F0

• All 00, All FF

• All FF, All 00

While the MBIST is running the digital core of the device is functional. The SPI interface can be used. It is not possible to use the CRAM

and DRAM.

7.5.2

LBIST

The LBIST is started by writing the LBIST password (0666h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)).

The overall LBIST operation takes about 32 ms (at 24 MHz) to complete. The coverage of the LBIST is > 92%.

The SPI interface is also covered by the LBIST. During the LBIST the device is no longer accessible via the SPI. When the LBIST is started

it takes control of the IRQB pin, which is used as a digital output signal to show the LBIST is busy. The IRQB pin is set low while the LBIST

is running. When the LBIST is finished, the IRQB signal goes high again.

The LBIST could fail in a way the IRQB signal never goes high again. In this case, the microcontroler needs to monitor this and reset the

device. When LBIST is finished (IRQB signal high), the device can be accessed by the SPI again and the LBIST result is available in the

BIST register (see Table 171, Bist_interface in read mode (1BDh)). After reading the results, the LBIST needs to be cleared by sending a

CLEAR command (refer to Table 170, Bist_interface in write mode (1BDh)). This releases the logic and the device returns to its original

state. It is recommended to check if the LBIST result is reset to “00” to ensure the LBIST clear command was successful.

The LBIST can be interrupted by a hardware reset via the RESETB pin. There is a second way to stop the LBIST after it is started by

writing the LBIST password. This is done by setting the Flag0 input pin to high. There is information in the LBIST result indicating the LBIST

was stopped by Flag0. Also in this case, an LBIST clear command (C1A0h) has to be sent or the RESETB pin must be set low to return

to normal operation mode. The FLAG0 pin has a weak PD resistor. If the pin is not connected, the LBIST runs and cannot be stopped by

Flag0.

7.6

Reset sources

The device has three possible reset sources:

• the resetb input reset pin is driven low

• the poresetb (power on reset) signal generated by the internal voltage regulator, incase an undervoltage is detected on VCC2P5

• a SPIresetb request received through SPI, when the appropriate code is written to the “global reset registers” (refer to See SPIReset

global reset register 1 and 2 on page 126). It is kept asserted for a fixed time (333 ns) then it is released.

Reset source can be determined reading the Reset_source register (refer to Table 168, Reset_Source (1B7h)).

Figure 26. VCC2P5 and reset sources

CVCC2P5

POResetB

SPIResetB

ResetB

RSTB

logic

RESETB

AGND

VCC5

VCC2P5

Regulator

Power On

Reset

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