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PT2000 Datasheet(PDF) 71 Page - NXP Semiconductors |
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PT2000 Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 148 page  71 NXP Semiconductors PT2000 8.1.2.2 Access sequence to data RAM When the device is operating in single microcore mode, access slots to data RAM are granted according to Table 47. The clock divider = ck_per +1’ (refer to Table 136, Clock_Prescaler (1A0h)). Tlast represents the last time slot. Tother represent all time slots (if any) between T3 and Tlast. When the device is operating in dual microcore mode, access slots to data RAM are granted according to Table 48 Note that when ck_per is equal to 1 and dual microcore mode is enabled, there are some limitations for the DRAM access. As shown in Table 48 when “ck_per = 1” the SPI has no dedicated access slot to the DRAM. At the same time it is clear for most applications, both microcores do not have to access the DRAM every microcontroler clock cycle. It is possible to use some unused slots from the microcores for the SPI. The limit with the 12 MHz dual sequencing access to the data RAM: there is a strong limit on how many instructions in a row the data ram can access (load, store instructions). This limit depends on the SPI frequency used in the application. As a consequence, the microcore 0 and 1 must not block the DRAM access slots for longer than the given number of ck cycles minus 1. If this limit is achieved, it automatically be reported by the NXP IDE (compiler). Table 47. Data RAM access sequence (single microcore mode) Ck_per flash_enable T0 T1 T2 T3 Tother Tlast 1 1 SPI r/w uc0 -- -- 1 0 SPI r/w SPI r/w - - - - 2 1 SPI r/w SPI r/w uc0 - - - 2 0 SPI r/w SPI r/w SPI r/w - - - 3 1 SPI r/w SPI r/w SPI r/w uc0 - - 3 0 SPI r/w SPI r/w SPI r/w SPI r/w - - 4+ 1 SPI r/w SPI r/w SPI r/w SPI r/w SPI r/w uc0 4 0 SPI r/w SPI r/w SPI r/w SPI r/w SPI r/w SPI r/w Table 48. Data RAM Access Sequence (dual microcore mode) Ck_per flash_enable T0 T1 T2 T3 Teven Todd Cycle stealing when uc0/ 1 are in wait 11 uc1 uc0 SPI r/w 1 0 SPI r/w SPI r/w 2 1 uc1 SPI r/w uc0 SPI r/w 2 0 SPI r/w SPI r/w SPI r/w 3 1 uc1 SPI r/w SPI r/w uc0 - - SPI r/w 3 0 SPI r/w SPI r/w SPI r/w SPI r/w - - 4 1 uc1 SPI r/w SPI r/w SPI r/w SPI r/w uc0 SPI r/w 4 0 SPI r/w SPI r/w SPI r/w SPI r/w SPI r/w SPI r/w |
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