PT2000 datasheet(72/148 Pages) NXP

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NXP Semiconductors

PT2000

Table 49 shows the smallest period in

μs and ck (12 MHz) clock cycles between the address available and first read data bit for SPI read

access, which could occur based on a given SPI baud rate.

8.1.3

Signature unit

The task of the signature unit is to compute a checksum of the CRAM to detect possible memory corruption.

The computation is first started when the corresponding CRAM is locked by the pre_flash_enable (see Table 58, Flash_enable (100h,

120h, 140h)). When the computation is complete, the result of the computation is compared to the checksum registers (see Table 66,

checksum_h (108h, 128h, 148h)) and Table 67, checksum_l (109h, 129h, 149h)). These registers contain the golden checksum, provided

during the init phase through the SPI and calculated automatically by the PT2000 IDE.

If the result is correct, the signature unit sets the flash_enable bit (see Table 58, Flash_enable (100h, 120h, 140h)). If the result is not

correct, an interrupt (optional, refer to Table 58, Flash_enable (100h, 120h, 140h)) is issued towards the microcontroller and both

microcores accessing the same CRAM are disabled.

The signature unit can be disabled by writing the Checksum_failure_disable bit in the flash_enable_reg (refer to Table 58, Flash_enable

(100h, 120h, 140h)). When the signature is disabled, the flash_enable bit is set immediately after the pre_flash_enable bit and a failed

checksum causes only a warning (set the appropriate bit in the flash_enable register) without disabling code execution.

The computation requires a different time according to the ck_per value and to the code_width (refer to Table 65, code_width (107h, 127h,

147h)). The worst case computation time for a ck_per of 1 and higher (ck = cksys/2+1 or smaller) is 20 * tCKSYS * (code_width-2). For

example, for a completely used memory, a ck_per of 2 and a cksys clock frequency of 24 MHz (ck at 6.0 MHz), the computation takes

851

μs.

The signature unit works only for a code width of 3 or larger. If a shorter code of 1 to 2 words is used, the signature unit has to be disabled.

8.1.4

SPI backdoor

It is also possible to access (both to read and to write) to all the registers normally accessible through the SPI by using an SPI backdoor.

Both the SPI read and write operations are multi cycle operations. Table 51 shows the number of cycles needed. The registers must not

be changed while the operation is in progress.

To read an SPI register, first the 8 LSBs of the address must be provided in the 8 LSBs of the “SPI address” at internal memory map

address. A read operation must then be requested with the “rdspi” instruction (refer to programming guide). The result is available at the

“SPI data” address of the internal memory map.

To write an SPI register, first the 8 LSBs of the address must be provided in the 8 LSBs of the “SPI address” address and the data to write

must be provided at the “SPI data” address. Then a write operation must be requested with the “wrspi” instruction (refer to programming

guide).

There are some access limitations when requesting write access to SPI registers via the SPI backdoor:

• First of all, it is only possible to write to SPI registers which are not locked at the moment the write operation “wrspi” is requested.

• For some special registers there are additional limitations dependant on the configuration of the device. Table 51 shows the different

limitations.

Table 49. SPI baud rate and DRAM access sequence for the ck_prescaler = “1”

SPI baud rate (MHz)

Minimum SPI read address to first read data bit delay (5 bits)

μs

ck Cycles (12 MHz)

1.0

5.0

2.0

2.5

4.0

1.25

8.0

0.625

7.5

0.5

6.0

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