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TDF8599B Datasheet(PDF) 29 Page - NXP Semiconductors |
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TDF8599B Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 54 page ![]() NXP Semiconductors TDF8599B I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with load diagnostics TDF8599B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 2 — 23 August 2016 29 / 54 Symbol Parameter Conditions Min Typ Max Unit Zth(load) load detection threshold impedance for normal speaker load; DB1[D4] = 0; DB2[D4] = 0 - - 25 Ω Zth(open) open load detection threshold impedance DB1[D4] = 1; DB2[D4] = 1 350 - - Ω AC load detection levels: I2C-bus mode only Ith(o)det(load)AC AC load detection output threshold current 250 500 700 mA Start-up/shut-down/mute timing twake wake-up time on pin EN before first I2C-bus transmission is recognized [7] - - 500 μs tdet(DCload) DC load detection time CON = 470 nF [7] - 380 - ms td(stb-mute) delay time from standby to mute measured from amplifier enabling to start of unmute (no DC load detection); CSVRR = 47 μF CON = 470 nF - 140 - ms td(mute-fgain) mute to full gain delay time CON = 470 nF [5] - 15 - ms shutdown delay time from EN pin LOW to SVRR LOW; voltage on pin SVRR < 0.1 V; CSVRR = 47 μF 200 350 550 ms shutdown delay time from EN pin LOW to SVRR LOW; voltage on pin SVRR < 0.1 V; CSVRR = 47 μF; VP = 35 V 300 400 700 ms shutdown hold delay time from pin EN LOW to ACGND LOW; voltage on pin ACGND < 0.1 V; Master mode - 370 - ms td delay time hold delay in Master mode to allow slaved devices to shutdown fosc = 320 kHz - 50 - ms Speaker load impedance at supply voltage equal to or below 24 V stereo mode 1.6 4 - Ω RL load resistance parallel mode 0.8 - - Ω [1] Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9. [2] Maximum leakage current from DCP pin to ground = 3 µA [3] The output offset values can be either positive or negative. The Vth(offset) limit values (excluding Typ) are the valid absolute values. [4] DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode. [5] The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin. [6] The DC load valid bit DB1[D6] must be used; Section 8.6.2.1. The DC load enable bit IB2[D2] must be reset after each load detection cycle to prevent amplifier hang-up incidents. [7] I2C-bus mode only. |
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