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TDF8599B Datasheet(PDF) 7 Page - NXP Semiconductors

Part # TDF8599B
Description  I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with load diagnostics
PDF  54 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDF8599B Datasheet(HTML) 7 Page - NXP Semiconductors

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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with
load diagnostics
TDF8599B
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2 — 23 August 2016
7 / 54
Table 4. I2C-bus mode operation
Pin EN
Pin SEL_MUTE Bit IB1[D0]
Bit IB2[D0]
Mode
HIGH
1
0
Operating mode
LOW
1
1
Mute mode
HIGH (S2 closed)
LOW
0
X[1]
Standby mode
LOW (S2 open)
X[1]
X[1]
X[1]
off (default)
[1]
X = do not care
Table 5. Non-I2C-bus mode operation
Pin EN
Pin SEL_MUTE
Mode
HIGH (S1 open)
Operating mode
HIGH (S2 closed)
LOW (S1 closed)
Mute mode (default)
LOW (S2 open)
X[1]
off
[1]
X = do not care
8.3 Pulse-width modulation frequency
The output signal from the amplifier is a PWM signal with a clock frequency of fosc. This
frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND. The
optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a resistor
with a value of 39 kΩ, for example, sets the clock frequency to 320 kHz (see Figure
5). The external capacitor (Cosc) has no influence on the oscillator frequency. It does
however, reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodulation
filter in the application generates an analog audio signal across the loudspeaker.
8.3.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8599B devices are daisy-chained
together in one audio application with a single device providing the clock frequency signal
for all other devices. In this situation, it is recommended that the oscillators of all devices
are synchronized for optimum EMI behavior as follows:
All OSCIO pins are connected together and one TDF8599B in the application is
configured as the clock-master. All other TDF8599B devices are configured as clock-
slaves (see Figure 5).
• The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8599B is in Master
mode.
• The clock-slave pins OSCIO are configured as the oscillator inputs. When pin OSCSET
is directly connected to pin AGND (see Table 6), the TDF8599B is in Slave mode.



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