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OM8373 Datasheet(PDF) 13 Page - NXP Semiconductors

Part # OM8373
Description  TV signal processor- Closed Caption decoder with embedded m-Controller
PDF  108 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

OM8373 Datasheet(HTML) 13 Page - NXP Semiconductors

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2004 Jan 15
13
Philips Semiconductors
Tentative Device Specification
TV signal processor-Closed Caption
decoder with embedded
µ-Controller
OM8373; OM8378
ECC
Enable Closed Caption Interrupt.
ET1
Enable Timer 1 Interrupt.
EX1
Enable External Interrupt 1.
ET0
Enable Timer 0 Interrupt.
EX0
Enable External Interrupt 0.
IEN1
-------
ET2
00H
ET2
Enable Timer 2 Interrupt.
IP
-
PBUSY
PES2
PCC
PT1
PX1
PT0
PX0
00H
PBUSY
Priority EBUSY Interrupt.
PES2
Priority ES2 Interrupt.
PCC
Priority ECC Interrupt.
PT1
Priority Timer 1 Interrupt.
PX1
Priority External Interrupt 1.
PT0
Priority Timer 0 Interrupt.
PX0
Priority External Interrupt 0.
IP1
-------
PT2
00H
PT2
Priority Timer 2 Interrupt.
P0
Reserved
P0<6>
P0<5>
Reserved
Reserved
Reserved
Reserved
Reserved
60H
P0<6:5>
Port 0 I/O register connected to external pins.
P1
P1<7>
P1<6>
Reserved
Reserved
P1<3>
P1<2>
P1<1>
P1<0>
CFH
P1<7:6>
Port 1 I/O register connected to external pins.
P1<3:0>
Port 1 I/O register connected to external pins.
P2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P2<0>
3FH
P2<0>
Port 2 I/O register connected to external pins.
P3
Reserved
Reserved
Reserved
Reserved
P3<3>
P3<2>
P3<1>
P3<0>
0FH
P3<3:0>
Port 3 I/O register connected to external pins.
P0CFGA
Reserved
P0CFGA<6>
P0CFGA<5>
Reserved
Reserved
Reserved
Reserved
Reserved
FFH
P0CFGB
Reserved
P0CFGB<6>
P0CFGB<5>
Reserved
Reserved
Reserved
Reserved
Reserved
00H
P0CFGB<x>/P0CFGA<x> = 00
MODE 0 Open Drain.
P0CFGB<x>/P0CFGA<x> = 01
MODE 1 Quasi Bi-Directional.
P0CFGB<x>/P0CFGA<x> = 10
MODE2 High Impedance.
P0CFGB<x>/P0CFGA<x> = 11
MODE3 Push Pull.
P1CFGA
P1CFGA<7>
P1CFGA<6>
Reserved
Reserved
P1CFGA<3>
P1CFGA<2>
P1CFGA<1>
P1CFGA<0>
FFH
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 2
SFR Bit description



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