OM8373 datasheet(28/108 Pages) PHILIPS

28 / 108 page

2004 Jan 15

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Closed Caption

decoder with embedded

µ-Controller

OM8373; OM8378

‘558 nominal mode’ (iic_lut=”00”)

This option accommodates the 558 I2C. The various serial

rates are shown below: -

‘558 fast mode’ (iic_lut=”01”)

This option accommodates the 558 I2C doubled rates as

shown below: -

‘558 slow mode’ (iic_lut=”10”)

This option accommodates the 558 I2C rates divided by 2

as shown below: -

Note: In the above tables the fclk relates to the clock rate of

the 80c51 IIC module (6MHz).

I2C Port Enable

One external I2C port is available. This port is enabled

using TXT21.I2C PORT EN. Any information transmitted

to the device can only be acted upon if the port is enabled.

Internal communication between the 80c51

micro-controller and the TV Signal Processor will continue

regardless of the value written to TXT21.I2C PORT EN.

LED Support

Port pins P0.5 and P0.6 have a 8mA current sinking

capability to enable LEDs in series with current limiting

resistors to be driven directly, without the need for

additional buffering circuitry.

MEMORY INTERFACE

The memory interface controls the access and refresh of

the embedded Display DRAM memory. The DRAM is

shared between the Display and Microcontroller sections.

The Display reads OSD/Closed Caption information from

the DRAM and converts it to RGB output values. The

Microcontroller uses the DRAM as embedded auxiliary

RAM.

Data Capture

The Data Capture section takes in the analogue

Composite Video and Blanking Signal (CVBS) from One

Chip, and from this extracts the required data, which is

then decoded and stored in SFR memory.

The extraction of the data is performed in the digital

domain. The first stage is to convert the analogue CVBS

signal into a digital form. This is done using an ADC

sampling at 12MHz. The data and clock recovery is then

performed by a Multi-Rate Video Input Processor

(MulVIP). From the recovered data and clock the following

data types is extracted: Line Twenty-One Data Services

(Closed Caption).

Data Capture Features

• Video Signal Quality detector.

• Data Capture for US Line 21 Data Services (Closed

Caption).

CR2

CR1

CR0

fclk (6MHz)

divided by

I2C Bit Frequency

(KHz) at fclk

000

100

1600

3.75

150

200

240

3200

1.875

160

37.5

120

Table 5

IIC Serial Rates ‘558 nominal mode’

CR2

CR1

CR0

fclk (6MHz)

divided by

I2C Bit Frequency

(KHz) at fclk

200

800

7.5

300

011

400

120

1600

3.75

111

100

Table 6

IIC Serial Rates ‘558 fast mode’

CR2

CR1

CR0

fclk (6MHz)

divided by

I2C Bit Frequency

(KHz) at fclk

120

3200

1.875

011

100

480

12.5

6400

0.9375

Table 7

IIC Serial Rates ‘558 slow mode’

320

18.75

240

CR2

CR1

CR0

fclk (6MHz)

divided by

I2C Bit Frequency

(KHz) at fclk

Table 7

IIC Serial Rates ‘558 slow mode’

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