OM8373 datasheet(22/108 Pages) PHILIPS

22 / 108 page

2004 Jan 15

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Closed Caption

decoder with embedded

µ-Controller

OM8373; OM8378

External (Auxiliary + Display) Memory

The normal 80C51 external memory area has been

mapped internally to the device, this means that the MOVX

instruction accesses data memory internal to the device.

The movx memory map is shown in Fig.5.

Auxiliary RAM Page Selection

The Auxiliary RAM page pointer is used to select one of

the 256 pages within the movx address space, not all

pages are allocated, refer to Fig.6. A page consists of 256

consecutive bytes. XRAMP only works on internal MOVX

memory.

Power-on Reset

Power on reset is generated internally to the TV processor,

hence no external reset circuitry is required. The TV

processor die shall generate the master reset in the

system, which in turn will reset the micro-controller die.

A external reset pin is still present and is logically "OR"-ed

with the internal Power on reset. This pin will only be used

for test modes and OTP programming. The active high

reset pin incorporates an internal pull-down, thus it can be

left unconnected in application.

Power Saving modes of Operation

There are three Power Saving modes, Idle, Stand-by and

Power Down, incorporated into the Painter die. When

utilizing either mode, the 3.3v power to the device (Vddp,

Vddc & Vdda) should be maintained, since Power Saving

is achieved by clock gating on a section by section basis.

STAND-BY MODE

During Stand-by mode, the Acquisition and Display

sections of the device are disabled. The following

functions remain active:-

• 80c51 CPU Core

• Memory Interface

• I2C

• Timer/Counters

• WatchDog Timer

• SAD and PWMs

To enter Stand-by mode, the STAND-BY bit in the

ROMBANK register must be set. Once in Stand-By, the

XTAL oscillator continues to run, but the internal clock to

Acquisition and Display are gated out. However, the clocks

to the 80c51 CPU Core, Memory Interface, I2C,

Timer/Counters, WatchDog Timer and Pulse Width

Modulators are maintained. Since the output values on

RGB and VDS are maintained the display output must be

disabled before entering this mode.

This mode may be used in conjunction with both Idle and

Power-Down modes. Hence, prior to entering either Idle or

Power-Down, the STAND-BY bit may be set, thus allowing

wake-up of the 80c51 CPU core without fully waking the

entire device (This enables detection of a Remote Control

source in a power saving mode).

IDLE MODE

During Idle mode, Acquisition, Display and the CPU

sections of the device are disabled. The following

functions remain active:-

• Memory Interface

• I2C

Data RAM

0000H

08FFH

0900H

7FFFH

8000H

84FFH

Display RAM

for

Closed Caption

8700H

871FH

CLUT

87F0H

87FFH

Display Registers

8800H

8A3FH

Dynamically

Re-definable

Characters

Lower 32K bytes

Upper 32K bytes

8A40H

FFFFH

Fig.5 Movx Memory Map

(XRAMP)=00H

0000H

00FFH

0100H

01FFH

00H

FFH

00H

FFH

(XRAMP)=01H

(XRAMP)=FEH

FE00H

FEFFH

FF00H

FFFFH

00H

FFH

00H

FFH

(XRAMP)=FFH

MOVX @DPTR,A

MOVX @Ri, A

MOVX A, @Ri

MOVX A,@DPTR

Fig.6 Indirect addressing

(Movx address space)

OM8373 Datasheet(PDF) 22 Page - NXP Semiconductors

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