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OM8373 Datasheet(PDF) 20 Page - NXP Semiconductors

Part # OM8373
Description  TV signal processor- Closed Caption decoder with embedded m-Controller
PDF  108 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

OM8373 Datasheet(HTML) 20 Page - NXP Semiconductors

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2004 Jan 15
20
Philips Semiconductors
Tentative Device Specification
TV signal processor-Closed Caption
decoder with embedded
µ-Controller
OM8373; OM8378
CHAR
SIZE<1:0>
Character matrix size.
00 - 10 lines per character matrix.
01 - 13 lines per character matrix.
10 - 16 lines per character matrix.
11 - 18 lines per character matrix.
NOTE: Character matrix width defined by TXT10.CHAR16/12.
CCON
0 - Closed Caption acquisition off.
1 - Closed Caption acquisition on.
I2C PORT EN
0 - Disable I2C PORT.
1 - Enable I2C PORT selection (P1.7/SDA0, P1.6/SCL0).
TXT22
GPF1<7>
GPF1<6>
GPF1<5>
GPF1<4>
GPF1<3>
GPF1<2>
GPF1<1>
GPF1<0>
XXH
GPF1<7:0>
General purpose register, bits defined by mask programmable bits.
GPF1<6>
0 - Painter Extended Fonts disabled.
1 - Painter Extended Fonts enabled.
GPF1<5>
Reserved.
GPF1<4> (Used
for software only)
Reserved.
GPF1<3>
0 - PWM0, PWM1, PWM2 & PWM3 output on Port 3.0 to Port 3.3 respectively.
1 - PWM0, PWM1, PWM2 & PWM3 output on Port 2.1 to Port 2.4 respectively.(not available on SDIP64)
GPF1<2>
0 - Closed Caption acquisition disabled.
1 - Closed Caption acquisition enabled.
GPF1<1>
Reserved.
GPF<0> (Polarity
reversed in
P_Leader
standalone)
0 - Standalone (Painter) mode.
1 - TV processor mode.
TXT31
----
GPF1<11>
GPF1<10>
GPF1<9>
GPF1<8>
XXH
GPF1<11:8>
General purpose register, bits defined by mask programmable location.
GPF1<10>
Reserved.
GPF1<9:8>
Reserved.
TXT32
GPF1<11>
GPF2<11>
GPF2<10>
GPF2<9>
GPF2<8>
GPF2<7>
GPF2<6>
GPF2<5>
XXH
GPF2<11:5>
Mask programmable bits available for TV processor configuration.
TXT33
GPF3<7>
GPF3<6>
GPF3<5>
GPF3<4>
GPF3<3>
GPF3<2>
GPF3<1>
GPF3<0>
XXH
GPF3<7:0>
Mask programmable bits available for TV processor configuration.
TXT34
----
GPF3<11>
GPF3<10>
GPF3<9>
GPF3<8>
XXH
GPF3<11:8>
Mask programmable bits available for TV processor configuration.
TXT37
0
0
TV LINE
SPACE<2>
TV LINE
SPACE<1>
TV LINE
SPACE<0>
CHAR
SPACE<2>
CHAR
SPACE<1>
CHAR
SPACE<0>
00H
TV LINE
SPACE<2:0>
No. of TV Lines between character row (0-7 TV Lines).
NOTE: Works in addition to TV display lines per character row (TXT21).
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 2
SFR Bit description



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