OM8373 datasheet(17/108 Pages) PHILIPS

17 / 108 page

2004 Jan 15

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Closed Caption

decoder with embedded

µ-Controller

OM8373; OM8378

TF1

Timer 1 overﬂow Flag. Set by hardware on Timer/Counter overﬂow.Cleared by hardware when processor vectors to interrupt routine.

TR1

Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off.

TF0

Timer 0 overﬂow Flag. Set by hardware on Timer/Counter overﬂow.Cleared by hardware when processor vectors to interrupt routine.

TR0

Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off.

IE1

Interrupt 1 Edge ﬂag (both edges generate ﬂag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt

processed.

IT1

Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.

IE0

Interrupt 0 Edge l ﬂag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.

IT0

Interrupt 0 Type ﬂag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts.

TDACH

TPWE

TD<13>

TD<12>

TD<11>

TD<10>

TD<9>

TD<8>

40H

TPWE

0 - Disable Tuning Pulse Width Modulator.

1 - Enable Tuning Pulse Width Modulator.

TD<13:8>

Tuning Pulse Width Modulator High Byte.

TDACL

TD<7>

TD<6>

TD<5>

TD<4>

TD<3>

TD<2>

TD<1>

TD<0>

00H

TD<7:0>

Tuning Pulse Width Modulator Low Byte.

TH0

TH0<7>

TH0<6>

TH0<5>

TH0<4>

TH0<3>

TH0<2>

TH0<1>

TH0<0>

00H

TH0<7:0>

Timer 0 high byte.

TH1

TH1<7>

TH1<6>

TH1<5>

TH1<4>

TH1<3>

TH1<2>

TH1<1>

TH1<0>

00H

TH1<7:0>

Timer 1 high byte.

TL0

TL0<7>

TL0<6>

TL0<5>

TL0<4>

TL0<3>

TL0<2>

TL0<1>

TL0<0>

00H

TL0<7:0>

Timer 0 low byte.

TL1

TL1<7>

TL1<6>

TL1<5>

TL1<4>

TL1<3>

TL1<2>

TL1<1>

TL1<0>

00H

TL1<7:0>

Timer 1 low byte.

TMOD

GATE

C/T

GATE

C/T

00H

Timer / Counter 1

Timer / Counter 0

GATE

Gating Control Timer /Counter 1.

C/T

Counter/Timer 1 selector.

M1,M0

Mode control bits Timer/Counter 1.

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.

M1,M0 = 01, 16 bit time interval or event counter.

M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overﬂow. Reload value stored in TH1.

M1,M0 = 11, stopped.

GATE

Gating control Timer/Counter 0.

C/T

Counter/Timer 0 selector.

Names

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

Table 2

SFR Bit description

OM8373 Datasheet(PDF) 17 Page - NXP Semiconductors

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