OM8373 datasheet(24/108 Pages) PHILIPS

24 / 108 page

2004 Jan 15

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Closed Caption

decoder with embedded

µ-Controller

OM8373; OM8378

edges of signal transitions. This is the default mode of

operation of the pads after reset.

High Impedance

The high impedance mode can be used for Input only

operation of the port. When using this configuration the two

output transistors are turned off.

Push-Pull

The push pull mode can be used for output only. In this

mode the signal is driven to either 0V or VDDp, which is

nominally 3.3V.

Interrupt System

The device has 8 interrupt sources, each of which can be

enabled or disabled. When enabled, each interrupt can be

assigned one of two priority levels. There are four

interrupts that are common to the 80C51, two of these are

external interrupts (EX0 and EX1) and the other two are

timer interrupts (ET0 and ET1). There is also one interrupt

connected to the 80c51 micro-controller IIC peripheral for

Transmit and Receive operation.

The TV processors have an additional 16-bit Timer (with

8-bit Pre-scaler). To accommodate this, another interrupt

ET2PR has been added to indicate timer overflow.

In addition to the conventional 80c51, two application

specific interrupts are incorporated internal to the device

which have the following functionality:-

CC (Closed Caption Data Ready Interrupt) - This

interrupt is generated when the device is configured for

Closed Caption acquisition. The interrupt is activated at

the end of the currently selected Slice Line as defined in

the CCLIN SFR.

BUSY (Display Busy Interrupt) - An interrupt is

generated when the Display enters either a Horizontal or

Vertical Blanking Period. i.e. Indicates when the

micro-controller can update the Display RAM without

causing undesired effects on the screen. This interrupt can

be configured in one of two modes using the MMR

Configuration Register (Address 87FF, Bit-3 [TXT/V]):-

• TeXT Display Busy: An interrupt is generated on each

active horizontal display line when the Horizontal

Blanking Period is entered.

• Vertical Display Busy: An interrupt is generated on each

vertical display field when the Vertical Blanking Period is

entered.

INTERRUPT ENABLE STRUCTURE

Each of the individual interrupts can be enabled or

disabled by setting or clearing the relevant bit in the

interrupt enable SFRs (IE and IEN1). All interrupt sources

can also be globally disabled by clearing the EA bit (IE.7).

INTERRUPT ENABLE PRIORITY

Each interrupt source can be assigned one of two priority

levels. The interrupt priorities are defined by the interrupt

priority SFRs (IP and IP1). A low priority interrupt can be

interrupted by a high priority interrupt, but not by another

low priority interrupt. A high priority interrupt can not be

interrupted by any other interrupt source. If two requests of

different priority level are received simultaneously, the

request with the highest priority level is serviced. If

requests of the same priority level are received

simultaneously, an internal polling sequence determines

which request is serviced. Thus, within each priority level

there is a second priority structure determined by the

polling sequence as defined in Table 3.

INTERRUPT VECTOR ADDRESS

The processor acknowledges an interrupt request by

executing a hardware generated LCALL to the appropriate

servicing routine. The interrupt vector addresses are

shown in Table 3.

Source

Priority within level

Interrupt Vector

EX0

Highest

0003H

ET0

000BH

EX1

0013H

ET1

001BH

ECC

0023H

ES2

002BH

EBUSY

0033H

ET2PR

Lowest

003BH

Table 3

Interrupt Priority (within same level)

EX0

ET0

EX1

ET1

ECC

ES2

EBUSY

Highest Priority Level1

Highest Priority Level0

ET2PR

Lowest Priority Level1

Lowest Priority Level0

IE.0:6

IP.0:6

Source

Enable

Global

Enable

Priority

Control

IE1.0

IP1.0

IE.7

Interrupt

Source

Fig.7 Interrupt Structure

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