OM8373 datasheet(25/108 Pages) PHILIPS

25 / 108 page

2004 Jan 15

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Closed Caption

decoder with embedded

µ-Controller

OM8373; OM8378

LEVEL/EDGE INTERRUPT

The external interrupt can be programmed to be either

level-activated or transition activated by setting or clearing

the IT0/1 bits in the Timer Control SFR(TCON).

The external interrupt INT1 differs from the standard

80C51 in that it is activated on both edges when in edge

sensitive mode. This is to allow software pulse width

measurement for handling remote control inputs.

Timer/Counter

Two 16 bit timers/counters are incorporated Timer0 and

Timer1. Both can be configured to operate as either timers

or event counters.

In Timer mode, the register is incremented on every

machine cycle. It is therefore counting machine cycles.

Since the machine cycle consists of 12 oscillator periods,

the count rate is 1/12 Fosc = 1MHz.

In Counter mode, the register is incremented in response

to a negative transition at its corresponding external pin

T0/1. Since the pins T0/1 are sampled once per machine

cycle it takes two machine cycles to recognise a transition,

this gives a maximum count rate of 1/24 Fosc = 0.5MHz.

There are six special function registers used to control the

timers/counters.

The Timer/Counter function is selected by control bits C/T

in the Timer Mode SFR (TMOD). These two

Timer/Counter have four operating modes, which are

selected by bit-pairs (M1.M0) in the TMOD. Refer to the

80C51 based 8-bit micro-controllers - Philips

Semiconductors (ref. IC20) for detail of the modes and

operation.

TL0/TL1 and TH0/TH1 are the actual timer/counter

registers for timer0 / timer1. TL0/TL1 is the low byte and

TH0/TH1 is the high byte.

ITx

Level

Edge

Active low

INT0 = Negative Edge

INT1 = Positive and Negative Edge

Table 4

External Interrupt Activation

TF1 TR TF0 TR

IE1 IT1 IE0 IT0

Symbol

Position

Name and Signiﬁcance

TF1

TCON.7

Timer 1 overﬂow ﬂag. Set by hard-

ware on timer/counter overﬂow.

Cleared by hardware when processor

vectors to interrupt routine.

TR1

TCON.6

Timer 1 Run control bit. Set/cleared

by software to turn timer.counter

on/off.

TF0

TCON.5

Timer 0 overﬂow ﬂag. Set by hard-

ware on timer/counter overﬂow.

Cleared by hardware when processor

vectors to interrupt routine.

TR0

TCON.4

Timer 0 Run control bit. Set/cleared

by software to turn timer.counter

on/off.

Symbol

Position

Name and Signiﬁcance

IE1

TCON.3

Interrupt 1 Edge ﬂag. Set by hardware

when external interrupt edge

detected. Cleared when interrupt

processed.

IT1

TCON.2

Interrupt 1 Type control bit.

Set/cleared by software to specify fall-

ing edge/low level triggered external

interrupts.

IE0

TCON.1

Interrupt 0 Edge ﬂag. Set by hardware

when external interrupt edge

detected. Cleared when interrupt

processed.

IT0

TCON.0

Interrupt 0 Type control bit.

Set/cleared by software to specify fall-

ing edge/low level triggered external

interrupts.

Fig.8 Timer/Counter Control (TCON) register

Gat C/T M1

M0 Gat C/T M1

Timer 1

Timer 0

Gate

Gating control when set. Timer/counter is enabled only

while px_int_n is high and TR control bit is set. When

cleared timer/counter is enabled whenever TR control bit

is set.

C/T

Timer or Counter selector. Cleared for timer operation

(input from system clock). Set for counter operation (input

from T input pin.

Operating

8048 Timer, TL serves as 5-bit prescaler.

16-bit Timer/Counter, TL and TH are cascaded.

8-bit auto-reload Timer/Counter, TH holds a value

which is to be loaded into TL.

timer 0: two 8-bit Timers/Counters. TL0 is controlled by

timer 0 control bits. TH0 is controlled by timer 1 control

bits. timer 1: stopped.

Fig.9 Timer/Counter Mode control (TMOD) register

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