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TMP1827 Datasheet(PDF) 32 Page - Texas Instruments

Part # TMP1827
Description  TMP1827 Single-Wire, ±0.3°C Accurate Temperature Sensor With SHA-256-HMAC Authentication Engine, 2-kbit EEPROM
PDF  68 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMP1827 Datasheet(HTML) 32 Page - Texas Instruments

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respond. If none of the devices have an alarm condition, then the host shall get all '1' followed by '1' on the bus
and host can send a bus reset subsequently. If the device sends a '1' followed by '0', the host shall interpret it as
either one or more devices have an alert condition, or all devices have an alert condition. If there is a bus noise,
that causes the line to be sample erroneously, but if no device has an alert condition, then the host shall get all
'1' on the bus during the address search phase.
Only devices that have an alert set shall participate when they receive an ALERTSEARCH address command
and shall respond by sending its 64-bit address. A device shall no longer participate in the send address phase
if it successfully transmits the device address, which automatically clears the internal alert flags, unless another
temperature conversion results in the alert condition getting set.
8.4.3.2.5 SKIPADDR (CCh)
The host can issue this command to select all the devices on the bus. This is useful when the host wants to write
to the scratchpad-1 or trigger the temperature conversion for all the devices on the bus. Additionally, the host
can use the command to increase the overall bus data throughput when there is a single device on the bus.
The host must take care to not issue the command when there are multiple devices on the bus,. If the host
intended to read the devices with this command, it would cause a collision on the bus.
8.4.3.2.6 OVD SKIPADDR (3Ch)
The host can issue this command to select all devices which support overdrive speed in a mixed speed bus.
This is useful when the host wants to write to the scratchpad-1 or trigger the temperature conversion for all
the devices on the bus that support overdrive speeds. Additionally, the host can use the command to increase
the overall bus data throughput when there is a single device on the bus. When the command is issued, only
devices that support overdrive mode shall set the internal OD flag as '1'.
The host must take care to not issue the command when there are multiple devices on the bus which support
overdrive mode. If the host intended to read the devices with this command, it would cause a collision on the
bus.
If the host issues a standard mode bus reset at any time, all devices which have OD flag set as '1' shall clear the
same and revert back to standard mode speed.
8.4.3.2.7 OVD MATCHADDR (69h)
The command is used by the host and is followed by a 64-bit address that is used to select a single device on
the bus in overdrive speed. The address for each device is unique, therefore only one device can be selected by
the command while all other devices have to wait for a bus reset. The selected device shall set its internal OD
flag as '1', and start all further communication in overdrive speed.
If the host issues a standard mode bus reset at any time, or selects another device using the OVD
MATCHADDR, then all other devices which have OD flag set as '1' shall clear the same and revert back to
standard mode speed.
8.4.3.2.8 FLEXADDR (0Fh)
The host issues the command to access a device by its short address that is configured in the short address
register. The short address itself is decoded by:
• Setting FLEX_ADDR_MODE[1:0] as '01b', for hardware address configured by IO0-IO3 tie off to either
VDD/SDQ or GND.
• Setting FLEX_ADDR_MODE[1:0] as '10b', for resistor address by connecting a resistor between ADDR and
GND.
• Setting FLEX_ADDR_MODE[1:0] as '11b', for combined IO and resistor address decoding.
Using the command does not affect the 64-bit unique address of the device. This command is followed by one
byte, which is the short address of the device, the host wants to select for further communication.
8.4.3.3 Function Phase
Figure 8-22, Figure 8-23 and Figure 8-24 show the function phase that follows the address phase. The host may
present different functions during this phase, which is followed by either the host sending data to the device,
TMP1827
SBOSA15 – SEPTEMBER 2022
www.ti.com
32
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Product Folder Links: TMP1827



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