TMP1827 datasheet(13/68 Pages) TI

13 / 68 page

8 Detailed Description

8.1 Overview

The TMP1827 is a digital output temperature sensor designed for thermal-management and thermal-protection

applications. The TMP1827 is a single-wire device which can operate in either supply powered or bus powered

(parasitic powered) mode. The device features a 2-kbit EEPROM, SHA-256-HMAC based authentication engine.

Figure 8-1 shows a block diagram of the TMP1827.

8.2 Functional Block Diagram

VDD

GND

SDQ

1-Wire Interface

Controller

ScratchPad-1

2 kbit User

EEPROM

Temperature

sensor circuit

Power Control &

Device Capacitor

ScratchPad-2

IO3

IO2/ALERT

IO1

IO0

Oscillator

Con gura on

EEPROM

ADC

Internal

thermal

BJT

Security

Controller

and SHA-256-

HMAC

Key and

Memory

Protec on

ADDR

Figure 8-1. Functional Block Diagram

8.3 Feature Description

8.3.1 Power Up

The device operates in both supply powered and bus powered mode. Irrespective of the mode, when the supply

voltage reaches within the operating range, the device requires tINIT to initialize itself. After tINIT, the host MCU

can begin accessing the device.

During initialization, the device may not respond to any bus activity. When initialization is complete, the device

shall wait for the bus reset from the host. During the initialization for the device, the following events take place:

• The EEPROM content for short address, temperature alert low, temperature alert high and temperature offset

registers are restored.

• The EEPROM for the IO configuration register is read and contents of the IO configuration register is

restored.

• The EEPROM content for device configuration-1 and device configuration-2 registers are restored to the

respective registers.

– If the ARB_MODE bits are set to value other than '00b', then the device will respond to the

SEARCHADDR in arbitration mode.

– If OD_EN bit is set to '1b', then the device shall communicate in overdrive speed, unless the first bus reset

pulse from the host is sent in standard speed.

• The user memory protection bits are restored and appropriate protection to the user EEPROM block applied.

• The authentication key and secret bytes are read from the EEPROM to internal flops for the authentication

operation.

8.3.2 Power Mode Switch

The device is designed to operate in supply powered or bus powered mode. The dual mode implementation

provides a unique method of redundancy that, even in cases where the power supply pin gets disconnected, the

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TMP1827

SBOSA15 – SEPTEMBER 2022

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