TMP1827 datasheet(16/68 Pages) TI

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8.3.6 Temperature Alert

The temperature alert feature uses the temperature alert low registers for low threshold comparison and

temperature alert high registers for high threshold comparison. The format of the register is the same as the

temperature results.

The device shall compare the result of the last conversion with the alert thresholds. If the temperature result

is less than the low limit, or more than the high limits, then the device shall set the appropriate alert status

flag for low or high temperature limits, in the status register. The alert status flags are cleared based on the

ALERT_MODE setting in the device configuration-1 register.

Additionally, if the IO2/ALERT pin is configured as an alert pin, the alert status is reflected on the pin.

8.3.7 Standard Device Address

Every device comes with a unique 64-bit address that is factory programmed. Additionally the device provides

flexible addressing modes that the host controller may use to improve bus throughput. This is described below.

8.3.7.1 Unique 64-Bit Device Address and ID

The device has a hard-coded, 64-bit address which is factory programmed and cannot be altered by the

customer application. The unique 64-bit device address is used for device addressing in the end application and

for NIST traceability. Figure 8-3 shows the format of the 64-bit address. When the host accesses the device or

when the device sends its address, the 64-bit unique address is sent least significant bit first. The unique 64-bit

address consists of 3 fields. The lower 8 bits consists of the device family code, followed by a 48-bit unique

number and 8-bit CRC checksum on the 56 bits preceding it.

The device family code for TMP1827 shall read as 27h.

8-bit Device Family

48-bit Unique Address

8-bit CRC

MSb

LSb

Bit-63

Bit-0

Figure 8-3. 64-Bit Device Address

8.3.8 Flexible Device Address

Depending on the user application case, the TMP1827 provides for some user and application configurable

address modes, called flexible address mode. These modes exist along side the standard device address, and is

extremely useful for applications that require a combination of faster access and device position identification.

When the flexible device address is used, the short address register is updated. The short address register shall

be updated by the host write when the FLEX_ADDR_MODE bits are '00b'. When these bits have a value other

than '00b', the resulting decode of the resistor connected on ADDR pin or IOs shall be overlaid on the short

address register. This is helpful as the same set of 16 resistors or 16 IO combinations can be used to extend the

number of unique flexible address up to 256.

The FLEX_ADDR_MODE is not backed in the configuration EEPROM. Hence after decoding, the host must

ensure that copy to configuration EEPROM is performed to make the short address values permanent, without

having to decode at every power up.

8.3.8.1 Non-Volatile Short Address

Figure 8-4 shows the user-programmable, 8-bit short address mode of the device. The host must program

the 8-bit short address to the underlying non-volatile memory, using a stand-alone programmer, so that at

subsequent power up, the device loads the short address and can respond to the host during the address phase

of bus communication.

TMP1827

SBOSA15 – SEPTEMBER 2022

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