TMP1827 datasheet(22/68 Pages) TI

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8.3.13 Bit Communication

The single-wire interface communication does not have a reference clock, therefore all communication is

performed asynchronously with fixed time slot (tSLOT) and variable pulse width to indicate logic '0' and '1'. In

idle state, the external pullup resistor holds the line high. All bit communication, whether it is a write or a read,

are initiated by the host by driving the data line low to generate a falling edge and the bit value is decoded as the

time for which the data line is held low or high after the falling edge.

Even though the communication is one bit at a time, the data exchanged between the host and device is

performed at byte boundary. Every byte is sent least significant bit first. The device behavior is not ensured when

incomplete bytes are sent.

8.3.13.1 Host Write, Device Read

A host write is the means by which the host sends the command, function, and data to the devices. A host write

starts by the host driving the data line low as shown in Figure 8-10. If the host intends to transmit a logic '1', the

line is released after tWR1L time. If the host intends to transmit a logic '0', the line is released after tWR0L. After

releasing the data, the pullup resistor causes the line to become high till the beginning of the next time slot. The

device samples the line after tRDV has elapsed from the falling edge, for a time frame indicated by tDSW. The host

must factor the rise time due to the pullup resistor and bus capacitance to determine the release of the data line

before the line is sampled by the device and the host drives the next write bit time slot.

VIL

VIH

VDD/VPUR

tWR1L

Host Write-1

tRDV

tDSW

VIL

VIH

tSLOT

tWR0L

Host Write-0

tRDV

tDSW

tREC

tSLOT

tREC

Host drives SDQ

High Impedance, external pullup

VDD/VPUR

Figure 8-10. Host Write, Device Read

8.3.13.2 Host Read, Device Write

A host read is the means by which the hosts gets the data from the device or the CRC for data integrity check. A

host read starts by the host driving the data line low as shown in Figure 8-11. When the device detects the falling

edge, the device can drive the line low before the time tRL. The host can release the bus from the side after the

time tRL(MIN) elapses. If the device intends to transmit a logic '1', then the bus is released before tRL(MAX) elapses.

If the device intends to transmit a logic '0', then the bus is released after tSLOT(MIN). The host must sample the

line after the time tRWAIT, for a time frame indicated by tMSW. The host must factor the rise time due to the pullup

resistor and bus capacitance to determine the sampling window for the host to sample the bit level sent by the

device or to drive the next read bit time slot.

TMP1827

SBOSA15 – SEPTEMBER 2022

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