TMP1827 datasheet(28/68 Pages) TI

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followed by a highly configurable address phase, where the host selects the device it wants to access. Finally,

there is a function phase where the host provides the selected device(s) the action it wants to take.

Reset

Command

Device Address

Function

Write Data

Reset Phase

Address Phase

Function Phase

Answer to

Reset

Read Data

CRC

Figure 8-19. Single-Wire Bus Communication

In a single-wire bus, all write and reads are initiated by the host except for the answer to reset which is initiated

by the devices on the bus.

8.4.3.1 Bus Reset Phase

The bus reset phase is the beginning of the communication. The phase is initiated by the host by holding the

single-wire data line low for a period tRSTL. All devices on the bus, irrespective of their current state shall respond

to the bus reset, by reinitializing their internal state and responding to the host initiated bus reset. The devices

respond after a minimum of tPDH, by holding the single-wire low for a time period of tRSTH as shown in Figure 7-1.

All devices are configured with the OD_EN bit set as '1' in the device configuration-2 register. If the host sends a

bus reset pulse of 48 µs to 80 µs, then only devices operating in overdrive speed shall respond to the bus reset

pulse, while devices operating in standard mode shall continue to wait for a standard mode bus reset.

If the host sends a bus reset pulse of minimum tRSTL for standard mode, the device shall reset the OD_EN bit

to '0' and respond to the bus reset in standard mode. If the bus consists of mixed standard and overdrive speed

devices, then sending a bus reset pulse in standard mode shall reset all devices to standard mode speed of

operation.

It is illegal for the host to send the bus reset for a particular speed of operation and then communicate at the

other speed mode. Also, if a bus reset pulse is sent which is greater than 80 µs (but less than 480 µs), then the

device shall be reset, though the device operation is not ensured.

8.4.3.2 Address Phase

Figure 8-20 shows the address phase that follows the bus reset phase. During this phase, the host presents 8-bit

commands which may be followed by either host sending a 64-bit device address, a 8-bit flexible address, or

skipping the address. Some of the commands are used to discover the device address, while others are used to

select the device.

TMP1827

SBOSA15 – SEPTEMBER 2022

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