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CS47L85 Datasheet(PDF) 265 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 265 Page - Cirrus Logic |
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265 / 370 page ![]() CS47L85 Rev 4.3 265 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4 EVENT5_FULL_ EINT1 0 Event Log 5 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 3 EVENT4_FULL_ EINT1 0 Event Log 4 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 2 EVENT3_FULL_ EINT1 0 Event Log 3 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 1 EVENT2_FULL_ EINT1 0 Event Log 2 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 0 EVENT1_FULL_ EINT1 0 Event Log 1 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. R6167 (1817h) IRQ1_Statu s_24 7 EVENT8_WMAR K_EINT1 0 Event Log 8 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 6 EVENT7_WMAR K_EINT1 0 Event Log 7 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 5 EVENT6_WMAR K_EINT1 0 Event Log 6 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 4 EVENT5_WMAR K_EINT1 0 Event Log 5 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 3 EVENT4_WMAR K_EINT1 0 Event Log 4 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 2 EVENT3_WMAR K_EINT1 0 Event Log 3 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 1 EVENT2_WMAR K_EINT1 0 Event Log 2 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 0 EVENT1_WMAR K_EINT1 0 Event Log 1 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. R6168 (1818h) IRQ1_Statu s_25 6 DSP7_DMA_EIN T1 0 DSP7 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 5 DSP6_DMA_EIN T1 00 DSP6 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 4 DSP5_DMA_EIN T1 00 DSP5 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 3 DSP4_DMA_EIN T1 00 DSP4 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 2 DSP3_DMA_EIN T1 00 DSP3 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. 1 DSP2_DMA_EIN T1 00 DSP2 DMA Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. |
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