CS47L85 datasheet(359/370 Pages) CIRRUS

359 / 370 page

CS47L85

Rev 4.3

359

RESETS SUMMARY

The contents of Table 138 provide a summary of the CS47L85 registers and other programmable memory under different

reset conditions. The associated events and conditions are listed below.



A Power-On Reset occurs when AVDD or DBVDD1 is below its respective reset threshold. (Note that DCVDD is

also required for initial start-up; subsequent interruption to DCVDD should only be permitted as part of a control

sequence for entering Sleep mode.)



A Hardware Reset occurs when the RESET

¯¯¯¯¯¯ input is asserted (logic 0).



A Software Reset occurs when register R0 is written to.



Sleep Mode is selected when LDO1 is disabled. Note that the AVDD, DBVDD1 and LDOVDD supplies must be

present, and the LDOENA pin held low. (It is assumed that DCVDD is supplied by LDO1.)

ALWAYS-ON

REGISTERS

OTHER

REGISTERS

CONTROL

SEQUENCER

MEMORY

DSP FIRMWARE

MEMORY

DSP1,2,3,4,5,7

DSP FIRMWARE

MEMORY

DSP6

Power-On Reset

Reset

Hardware Reset

Reset

Retained

(see note)

Software Reset

Reset

Retained

(see note)

Retained

(see note)

Sleep Mode

Retained

Reset

Table 138 Memory Reset Summary

See “Low Power Sleep Configuration” for details of Sleep Mode, and the ‘Always-On’ registers.

Note that, to retain the DSP firmware memory contents during Hardware Reset or Software Reset, it must be ensured that

DCVDD is held above its reset threshold. If DCVDD is powered from internal LDO, then it is recommended to assert the

LDOENA pin before the Reset, in order to maintain the DCVDD supply.

CS47L85 Datasheet(PDF) 359 Page - Cirrus Logic

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