AM625 datasheet(95/255 Pages) TI

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7.6 Operating Performance Points

This section describes maximum operating conditions of the device in Table 7-1 and describes each Operating

Performance Point (OPP) for processor clocks and device core clocks in Table 7-2.

Table 7-1. Device Speed Grades

Speed

Grade

VDD_CORE

(V)(1)

MAXIMUM OPERATING FREQUNCY (MHz)

MAXIMUM

TRANSITION

RATE (MT/s)(2)

A53SS

(Cortex-

A53x)

GPU

PRU

Main

Infra

(CBA)

MCUSS

(Cortex-

M4F)

Device/

Power

Manager

(Cortex-

R5F)

SMS

Subsystem

(Dual

Cortex-

M4F)

OCSRAM

DDR4

LPDDR4

0.75/0.85

300

500

250

400

1600

0.75/0.85

800

500

250

400

1600

0.75/0.85

1000

500

333

250

400

800

400

1600

0.75/0.85

1250

500

333

250

400

800

400

1600

0.85

1400

(1)

Nominal operating voltage, see Recommended Operating Conditions.

(2)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

Table 7-2. Device Operating Performance Points

OPP

A53SS(1)

FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)

MT/s(3)

GPU

PRU

MAIN

INFRA (CBA)

MCUSS

DEVICE/

POWER

MANAGER

SMS /

SMS CBA

OCSRAM

DDR4

LPDDR4

High

From

ARM0

PLL

Bypass

Speed

Grade

Maximum

500

333,

250,

200

250

400

200

400

1600

(Max)

From

DDR

PLL

Bypass(4)

1600

Low

N/A

125

133

250

(DRAM DLL

Bypass)

(1)

Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.

(2)

Fixed operating frequency, set by software at boot.

(3)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

(4)

The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL

Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.

7.7 Power Consumption Summary

For information on the device power consumption, see the AM62x Power Estimation Tool application note.

www.ti.com

AM625, AM623

SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022

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