AM625 datasheet(108/255 Pages) TI

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7.11.2.2.2 Power-Down Sequencing

Figure 7-6 describes the device power-down sequencing.

AM62x_ELCH_02

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

VSYS

VMON_VSYS

VSYS, VMON_VSYS

VPP

VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(1)

VDDSHV_CANUART , VDDA_3P3_USB,

(1)

VMON_3P3_SOC

VDDS_OSC0, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(2)

VDDSHV_CANUART , VDDA_MCU,

(2)

VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_OLDI0,

VDDA_1P8_USB, VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1,

VDD_CORE

, VDD_CANUART , VDDA_CORE_CSIRX0 , VDDA_CORE_USB ,

(3)(5)

(3)

VDDA_DDR_PLL0

(6)

VDD_CORE

, VDDR_CORE , VDDA_CANUART , VDDA_CORE_CSIRX0 ,

(5)

(4)(5)

(4)

(6)

VDDA_CORE_USB ,VDDA_DDR_PLL0

Hi-Z

VDDSHV4 , VDDSHV5 , VDDSHV6

(7)

VDDS_DDR, VDDS_DDR_C

Figure 7-6. Power-Down Sequencing

1. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 3.3V.

2. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 1.8V.

3. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when

operating at 0.75V.

4. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when

operating at 0.85V.

5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +

0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after

VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements

beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by

the same source so they ramp together when VDD_CORE is operating at 0.85V.

6. VDDA_DDR_PLL0 is connected to VDD_CORE inside the ALW package.

7. VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic

voltage change without any dependency on other power rails. This capability is required to support UHS-I

SD Cards.

AM625, AM623

SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022

www.ti.com

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